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2016 International SoC Design Conference (ISOCC)最新文献

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A study of META-voltage controlled oscillator and prescaler using 65nm CMOS process: META-VCO and prescaler using 65nm CMOS precess 采用65nm CMOS工艺的元压控振荡器和预分频器的研究:采用65nm CMOS工艺的元压控振荡器和预分频器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799701
N. Kwon, Bora Kim, Yong Moon
{"title":"A study of META-voltage controlled oscillator and prescaler using 65nm CMOS process: META-VCO and prescaler using 65nm CMOS precess","authors":"N. Kwon, Bora Kim, Yong Moon","doi":"10.1109/ISOCC.2016.7799701","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799701","url":null,"abstract":"The VCO (Voltage Controlled Oscillator) and the high speed prescaler are designed using 65nm CMOS technology with the frequency of 28.5GHz 5G mobile communication system. The simulation result show that the VCO has 28.4~28.8GHz tuning range and the prescaler divides the VCO output. The phase noise of the VCO is -173.75dBc/Hz at 1MHz and -181.43dBc/Hz at 10MHz offset frequency.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122138034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A design of real time detection IP with color detection for surveillance 一种用于监控的实时检测IP彩色检测的设计
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799809
Chang-Hee Park, Hyun-Tae Kim, Young-Min Jang, Sang-Bock Cho
{"title":"A design of real time detection IP with color detection for surveillance","authors":"Chang-Hee Park, Hyun-Tae Kim, Young-Min Jang, Sang-Bock Cho","doi":"10.1109/ISOCC.2016.7799809","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799809","url":null,"abstract":"In this paper, in order to implement the IP of edge detection algorithm for surveillance in image using the camera in CCTV or vehicle black box, we designed pre-processing step that is the edge extraction algorithm. First, after input image converts into the input signals of R, G, and B, three inputs are combined, and converted to gray scale. The data and blue color value are entered separated from each other and subtraction operations. Then appropriate portion by threshold extracts only white and converts the rest to black. A proposed algorithm was implemented using Matlab program. It was verified through a RTL-level simulation of ISE14.3.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117247371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pedestrian detection aided by temporal prior 基于时间先验的行人检测
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799837
Zhaowei Cai, Matthew Jacobsen, N. Vasconcelos
{"title":"Pedestrian detection aided by temporal prior","authors":"Zhaowei Cai, Matthew Jacobsen, N. Vasconcelos","doi":"10.1109/ISOCC.2016.7799837","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799837","url":null,"abstract":"In this paper, we developed an algorithm to construct temporal priors to improve the stability of pedestrian detections. The proposed temporal prior has no additional computation cost and could be applied to any image based pedestrian detector. We also present a FPGA implementation that can process VGA video at a frame rate of 30~40 frames per second in real time. The design is implemented on a Xilinx Zynq FPGA. It performs all steps of the algorithm in the FPGA fabric including: color space conversion, frame rescaling, HOG feature extraction, and candidate evaluation in a sliding window. The design uses parallel pipelines to evaluate multiple scales per frame.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124423983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area efficient neuromorphic circuit based on stochastic computation 基于随机计算的面积高效神经形态电路
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799739
Kiwon Yoon, Suhyeong Choi, Youngsoo Shin
{"title":"Area efficient neuromorphic circuit based on stochastic computation","authors":"Kiwon Yoon, Suhyeong Choi, Youngsoo Shin","doi":"10.1109/ISOCC.2016.7799739","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799739","url":null,"abstract":"Neuromorphic circuit can be simplified by applying stochastic computing, which uses a bit stream. A large number of stochastic number generators (SNGs) allows independent bit streams and hence secures accuracy, but outweighs the advantage of stochastic computing in circuit area. An area efficient SNG design method is proposed, in which a single linear feedback shift register (LFSR) is shared among a number of SNGs; independency of bit streams is made possible through shuffled wiring between LFSR and bit stream generators. Proposed design method is applied to a neuromorphic circuit that recognizes handwritten numbers; circuit area is reduced by 86% while prediction accuracy is sacrificed by 11% compared to a reference design in which LFSR is not shared.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124490600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nighttime image enhancement applying dark channel prior to raw data from camera 夜间图像增强应用暗通道之前，从相机的原始数据
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799836
Y. Gong, Yeejin Lee, Truong Q. Nguyen
{"title":"Nighttime image enhancement applying dark channel prior to raw data from camera","authors":"Y. Gong, Yeejin Lee, Truong Q. Nguyen","doi":"10.1109/ISOCC.2016.7799836","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799836","url":null,"abstract":"This paper presents an alternative approach to enhance visibility of images captured at night. In order to improve visual quality of nighttime image, we perform image enhancement in linear sensor space, which best represents image formation models. The analyses show that the proposed approach is helpful to reduce error amplification and computational complexity. In addition, experimental results verify that the proposed method enhances visibility for real-world dataset.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130002995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power and real-time computer vision on-chip 低功耗和实时计算机视觉芯片
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799731
Wei Pang, Hantao Huang, F. An, Hao Yu
{"title":"Low-power and real-time computer vision on-chip","authors":"Wei Pang, Hantao Huang, F. An, Hao Yu","doi":"10.1109/ISOCC.2016.7799731","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799731","url":null,"abstract":"Computer vision on chip is critical for many emerging applications such as advanced driver assistance system (ADAS), which requires a low-power and real-time image data analytics. Therefore, designing a computer-vision accelerator on-chip to achieve high throughput as well as low power is greatly needed. This paper reviews how to have ASIC realization of standard computer vision algorithms such as SIFT/SURF. The first work is a feature-based recognition co-processor with peak power consumption of 31.5mW for real-time recognition of VGA images. The second work is a face recognition accelerator with 23mW for 5.5 frame/s HD images.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130038513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Speed-adaptive ratio-based lane detection algorithm for self-driving vehicles 基于速度自适应比率的自动驾驶车辆车道检测算法
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799781
Seongrae Kim, Junhee Lee, Youngmin Kim
{"title":"Speed-adaptive ratio-based lane detection algorithm for self-driving vehicles","authors":"Seongrae Kim, Junhee Lee, Youngmin Kim","doi":"10.1109/ISOCC.2016.7799781","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799781","url":null,"abstract":"Lane detection algorithm using a vision sensor or a camera would be more effective for self-driving vehicles to keep in lane, if it is possible to derive a distance ratio between a vehicle and left-right lanes. However, a dangerous situation may occur if the performance of the camera (e.g., frame/sec.) and the real-time speed of the vehicle are not considered properly because of the huge distance difference among frames for a fast moving vehicle with a low-speed camera. In this study, we propose a simple method to anticipate the relative position of the vehicle in the following frame from the current frame image. The expected ratio between a vehicle and the left-right lanes can be obtained by using of the speed of a vehicle and the frame speed of a camera. Experiment results show that less than 5.28% error occurs by the proposed algorithm for various cars and cameras.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132471387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An ultra-low power AES encryption core in 65nm SOTB CMOS process 基于65nm SOTB CMOS工艺的超低功耗AES加密核心
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799747
Van‐Phuc Hoang, V. Dao, C. Pham
{"title":"An ultra-low power AES encryption core in 65nm SOTB CMOS process","authors":"Van‐Phuc Hoang, V. Dao, C. Pham","doi":"10.1109/ISOCC.2016.7799747","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799747","url":null,"abstract":"This paper presents an efficient ASIC implementation of the low area and ultra-low power AES encryption core with an optimized S-box, Rcon and control blocks optimization, combined with a simple clock gating technique using an ultra-low power 65nm SOTB CMOS technology. The ASIC implementation results show that the proposed AES encryption core requires a small number of clock cycles with ultra-low power consumption and achieves higher resource usage efficiency compared with other designs.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123143423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A fast-locking clock multiplying DLL 一个快速锁定时钟乘以DLL
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799773
Jongsun Kim, B. Bae
{"title":"A fast-locking clock multiplying DLL","authors":"Jongsun Kim, B. Bae","doi":"10.1109/ISOCC.2016.7799773","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799773","url":null,"abstract":"A fast-locking clock multiplying delay-locked loop (MDLL) for fractional-ratio frequency multiplication is presented. A new phase detecting controller (PDC) has been adopted to resolve the long locking time problem of conventional MDLLs. The proposed FMDLL was implemented in 65-nm CMOS process and occupies an active area of 0.015 mm2. It operates over a frequency range of 2.0-4.0 GHz with a frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while reducing locking time of about 75%.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low latency IFFT design for 3GPP LTE 3GPP LTE低延迟IFFT设计
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799737
Yeonjin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho
{"title":"Low latency IFFT design for 3GPP LTE","authors":"Yeonjin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho","doi":"10.1109/ISOCC.2016.7799737","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799737","url":null,"abstract":"In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed architecture was verified using Altera Modelsim.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121565469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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