Yeonjin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho
{"title":"3GPP LTE低延迟IFFT设计","authors":"Yeonjin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho","doi":"10.1109/ISOCC.2016.7799737","DOIUrl":null,"url":null,"abstract":"In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed architecture was verified using Altera Modelsim.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Low latency IFFT design for 3GPP LTE\",\"authors\":\"Yeonjin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho\",\"doi\":\"10.1109/ISOCC.2016.7799737\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed architecture was verified using Altera Modelsim.\",\"PeriodicalId\":278207,\"journal\":{\"name\":\"2016 International SoC Design Conference (ISOCC)\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2016.7799737\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2016.7799737","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed architecture was verified using Altera Modelsim.