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2016 International SoC Design Conference (ISOCC)最新文献

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Throughput enhancemnet with optimal fragmented MSDU size for fragmentation and aggregation scheme in WLANs 基于最佳碎片MSDU大小的无线局域网分片和聚合方案吞吐量提升
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799790
Eunbi Ku, Chulho Chung, Byungcheol Kang, Jaeseok Kim
{"title":"Throughput enhancemnet with optimal fragmented MSDU size for fragmentation and aggregation scheme in WLANs","authors":"Eunbi Ku, Chulho Chung, Byungcheol Kang, Jaeseok Kim","doi":"10.1109/ISOCC.2016.7799790","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799790","url":null,"abstract":"The fragmentation and aggregation (F&A) algorithm improves the throughput while ensuring the reliability in the MAC layer. To determining the optimal fragment size is a key issue of effectively operating the F&A algorithm. In this paper, the proposed method selects the optimal fragmented frame size and uses aggregation scheme based on various channel conditions. As a result the throughput can be further increased.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127940970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Memory efficient hardware accelerator for kernel support vector machine based pedestrian detection 基于核支持向量机的高效内存行人检测硬件加速器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799723
Asim Khan, C. Kyung
{"title":"Memory efficient hardware accelerator for kernel support vector machine based pedestrian detection","authors":"Asim Khan, C. Kyung","doi":"10.1109/ISOCC.2016.7799723","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799723","url":null,"abstract":"Pedestrian detection being a vital as well as complex problem poses a unique challenge from accuracy and complexity point of view. On-chip memory requirement is one of the key issues for sliding window based detectors. In this paper a memory efficient hardware architecture is proposed which estimates the weights from a partially stored model at runtime. It uses a simple and robust feature with histogram intersection classifier. The implementation results show 80% reduction in logic resources and 46% reduction in memory without sacrificing accuracy as compared to the state of the art hardware implementations.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134137154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A synchronous boost converter with high speed and high accuracy peak current control unit 一种具有高速、高精度峰值电流控制单元的同步升压变换器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799822
Shengpeng Tang, Xianzhi Meng, Donglie Gu, Jianxiong Xi, Lenian He, Kexu Sun
{"title":"A synchronous boost converter with high speed and high accuracy peak current control unit","authors":"Shengpeng Tang, Xianzhi Meng, Donglie Gu, Jianxiong Xi, Lenian He, Kexu Sun","doi":"10.1109/ISOCC.2016.7799822","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799822","url":null,"abstract":"A 3 MHz, 48W Boost converter with high speed and high accuracy Peak Current Control Unit (PCCU) is presented. The Boost controller IC adopts a novel PCCU consisting of a fully differential open-loop operational transconductance amplifier (OTA) and a trans-impedance amplifier (TIA), which can minimize the delay and error of the whole control loop. In the PCCU, the compensated output of error amplifier is moved forward to improve the control accuracy further. This IC is designed in CSMC 0.8 um 60 V BCD process. The simulation results show the Boost converter operates at 3 MHz and the peak current control error is 1.3% under the worst situation. The delay of peak current trigger point to the low side gate driver (LDRV) output is 25.14 ns and the delay of the compensated output of error amplifier to LDRV output is 37.56 ns.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A decouple structured gyroscope with integrated readout circuit on standard 0.18pm 1P6M CMOS technology 基于标准0.18pm 1P6M CMOS技术的解耦结构陀螺仪集成读出电路
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799718
Chun-Lin Chien, K. Wen
{"title":"A decouple structured gyroscope with integrated readout circuit on standard 0.18pm 1P6M CMOS technology","authors":"Chun-Lin Chien, K. Wen","doi":"10.1109/ISOCC.2016.7799718","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799718","url":null,"abstract":"A dual proof-mass structured gyroscope integrated with readout circuit have been proposed. The C to V stage is achieved by the differential difference amplifier (DDA) which has advantages of high gain, low temperature and process dependence. Chopper Stabilization (CHS) and Corrected Double Sampling (CDS) is used to suppress low-frequency noise and compensate DC offset. The gain of DDA is 25dB and power consumption of total readout circuit is 791μW. The mems part is fabricated with standard 1P6M 0.18um CMOS process and the mechanical sensitivity is 11.26aF/°/s. Chip area is 1.9×1.7mm2.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134392667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Artificial neural network implementation in FPGA: A case study 人工神经网络在FPGA中的实现:一个案例研究
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799795
Shuai Li, K. Choi, Yunsik Lee
{"title":"Artificial neural network implementation in FPGA: A case study","authors":"Shuai Li, K. Choi, Yunsik Lee","doi":"10.1109/ISOCC.2016.7799795","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799795","url":null,"abstract":"Artificial Neural Network (ANN) is very powerful to deal with signal processing, computer vision and many other recognition problems. In this work, we implement basic ANN in FPGA. Compared with software, the FPGA implementation can utilize parallelism to speedup processing time. Additionally, hardware implementation can save more power compared with CPU/GPU. Our ANN in FPGA has a high learning ability, for logical XOR problem, which reduced the error rate from 10-2 to 10-4.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133487740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Area-efficient and high-speed binary divider architecture for bit-serial interfaces 位串行接口的高效率高速二进制分频器结构
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799798
Yunho Park, Jong-Hoon Kwon, Youngjoo Lee
{"title":"Area-efficient and high-speed binary divider architecture for bit-serial interfaces","authors":"Yunho Park, Jong-Hoon Kwon, Youngjoo Lee","doi":"10.1109/ISOCC.2016.7799798","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799798","url":null,"abstract":"This paper proposes a low-complexity binary divider for high-speed serial interfaces. In contrast that the previous parallel dividers require a large amount of hardware costs, the proposed divider achieves a low-complexity division by targeting the serial interface that is widely used for the recent digital communications. By modifying the linear feedback shift register (LFSR) architecture for polynomial division, the high-speed processing element is newly introduced to handle the serialized dividend input. As a result, the proposed serialized architecture reduced the area-time complexity by 75 times compared to the previous slow parallel divider.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128904783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 11mV single stage thermal energy harvesting regulator with effective control scheme for extended peak load 11mV单级热能收集调节器，具有有效的扩展峰值负荷控制方案
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799711
V. Priya, Murali K. Rajendran, Shourya Kansal, A. Dutta
{"title":"A 11mV single stage thermal energy harvesting regulator with effective control scheme for extended peak load","authors":"V. Priya, Murali K. Rajendran, Shourya Kansal, A. Dutta","doi":"10.1109/ISOCC.2016.7799711","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799711","url":null,"abstract":"A thermo-electric energy harvesting based regulator system with output power maximization for high conversion ratio and very low input voltages, suitable for low power biomedical applications is presented. An optimal control topology for an inductor based regulator is implemented. Zero Current Switching is achieved by Pulse Width Modulation. Feedback mode control regulates output voltage to 1V with maximal load support. The system delivers peak power of 1.5mW and 19uW at 100mV and 11 mV input, respectively. The post-layout simulations done in UMC 180nm CMOS, show peak efficiency of 68% at 11mV input to boost converter.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131672815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
3D2 processing architecture — High reliability and low power computing for novel nano tactile sensor array 3d处理架构——用于新型纳米触觉传感器阵列的高可靠性和低功耗计算
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799856
K. Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, H. Yamauchi, Yoichiro Sato, H. Takao
{"title":"3D2 processing architecture — High reliability and low power computing for novel nano tactile sensor array","authors":"K. Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, H. Yamauchi, Yoichiro Sato, H. Takao","doi":"10.1109/ISOCC.2016.7799856","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799856","url":null,"abstract":"We have proposed new instrumental techniques to quantify human touch feelings by nano tactile sensor array system with 3D2 processing architecture. In the computation of quantification of human touch feelings, high-level semantics features are calculated from low-level features which are the result of FFT, wavelet translation, etc. For some application, especially medical application, high reliability is required for the recognition results. Furthermore, real-time processing and low power computing are also required. 3D2 Processing architecture provides high reliable and low power computing for the accelerator. The architecture has three features: Parallel Computation of Multiple Recognition Algorithms for High Reliability, Spatial-Parallel Temporal-Pipeline Streaming Processing for High Energy Efficiency Processing, and Current Reuse Energy Pipeline for Low Power Processing.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115557910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dense stereo-based real-time ROI generation for on-road obstacle detection 基于密集立体的道路障碍物检测实时ROI生成
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799840
Soon Kwon, Hyuk-Jae Lee
{"title":"Dense stereo-based real-time ROI generation for on-road obstacle detection","authors":"Soon Kwon, Hyuk-Jae Lee","doi":"10.1109/ISOCC.2016.7799840","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799840","url":null,"abstract":"The use of 3D visual information has become widespread as an essential cue for detecting on-road obstacles in ADAS. In this paper, we propose an accurate dense-stereo-based system for the generation of on-road obstacle ROIs. To balance the concerns of computation overhead and algorithm accuracy, this paper presents an efficient depth map generation that combines global stereo matching with depth up-sampling. The entire system has been implemented with a hardware and software partitioning method running on an FPGA and embedded CPU for real-time processing. The implementation results verify that the proposed stereo vision system efficiently outputs accurate ROI candidates for on-road obstacle detection.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114375727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A fully integrated high-efficiency step-up DC-DC converter for energy harvesting applications 一个完全集成的高效升压DC-DC转换器，用于能量收集应用
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799720
S. M. Noghabaei, M. Sawan
{"title":"A fully integrated high-efficiency step-up DC-DC converter for energy harvesting applications","authors":"S. M. Noghabaei, M. Sawan","doi":"10.1109/ISOCC.2016.7799720","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799720","url":null,"abstract":"In this paper, a novel low-voltage and fully integrated Step-up DC-DC converter for energy harvesting applications, designed in 130 nm CMOS technology is presented. Simulation results proved that the proposed step-up converter consisting of a differential cross-coupled architecture along with a latched charge pump enable us to boost up very low input voltages beyond 50 mV. The input voltage of 80 mV is converted to 1 V at a load resistance of 1 MΩ with a conversion efficiency of about 24%. The proposed converter consumes only 4.2-μW.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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