Area-efficient and high-speed binary divider architecture for bit-serial interfaces

Abstract

This paper proposes a low-complexity binary divider for high-speed serial interfaces. In contrast that the previous parallel dividers require a large amount of hardware costs, the proposed divider achieves a low-complexity division by targeting the serial interface that is widely used for the recent digital communications. By modifying the linear feedback shift register (LFSR) architecture for polynomial division, the high-speed processing element is newly introduced to handle the serialized dividend input. As a result, the proposed serialized architecture reduced the area-time complexity by 75 times compared to the previous slow parallel divider.