{"title":"一个快速锁定时钟乘以DLL","authors":"Jongsun Kim, B. Bae","doi":"10.1109/ISOCC.2016.7799773","DOIUrl":null,"url":null,"abstract":"A fast-locking clock multiplying delay-locked loop (MDLL) for fractional-ratio frequency multiplication is presented. A new phase detecting controller (PDC) has been adopted to resolve the long locking time problem of conventional MDLLs. The proposed FMDLL was implemented in 65-nm CMOS process and occupies an active area of 0.015 mm2. It operates over a frequency range of 2.0-4.0 GHz with a frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while reducing locking time of about 75%.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fast-locking clock multiplying DLL\",\"authors\":\"Jongsun Kim, B. Bae\",\"doi\":\"10.1109/ISOCC.2016.7799773\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast-locking clock multiplying delay-locked loop (MDLL) for fractional-ratio frequency multiplication is presented. A new phase detecting controller (PDC) has been adopted to resolve the long locking time problem of conventional MDLLs. The proposed FMDLL was implemented in 65-nm CMOS process and occupies an active area of 0.015 mm2. It operates over a frequency range of 2.0-4.0 GHz with a frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while reducing locking time of about 75%.\",\"PeriodicalId\":278207,\"journal\":{\"name\":\"2016 International SoC Design Conference (ISOCC)\",\"volume\":\"237 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2016.7799773\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2016.7799773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
提出了一种用于分数比倍频的快锁时钟乘延时锁环(MDLL)。采用一种新的相位检测控制器(PDC)来解决传统mdl锁相时间长的问题。所提出的FMDLL采用65纳米CMOS工艺实现，其有效面积为0.015 mm2。它在2.0-4.0 GHz的频率范围内工作，频率倍增系数为N/M，其中N = 4,5,8,10, M = 1,2,3。它在4ghz时实现了13.5 ps的峰值输出时钟抖动，同时减少了大约75%的锁定时间。
A fast-locking clock multiplying delay-locked loop (MDLL) for fractional-ratio frequency multiplication is presented. A new phase detecting controller (PDC) has been adopted to resolve the long locking time problem of conventional MDLLs. The proposed FMDLL was implemented in 65-nm CMOS process and occupies an active area of 0.015 mm2. It operates over a frequency range of 2.0-4.0 GHz with a frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while reducing locking time of about 75%.
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