Low-power and real-time computer vision on-chip

Computer vision on chip is critical for many emerging applications such as advanced driver assistance system (ADAS), which requires a low-power and real-time image data analytics. Therefore, designing a computer-vision accelerator on-chip to achieve high throughput as well as low power is greatly needed. This paper reviews how to have ASIC realization of standard computer vision algorithms such as SIFT/SURF. The first work is a feature-based recognition co-processor with peak power consumption of 31.5mW for real-time recognition of VGA images. The second work is a face recognition accelerator with 23mW for 5.5 frame/s HD images.