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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)最新文献

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Noise-insensitive approaches to two-dimensional system identification and texture image synthesis 二维系统识别与纹理图像合成的噪声不敏感方法
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822347
Chong-Yung Chi, Chii-Horng Chen
{"title":"Noise-insensitive approaches to two-dimensional system identification and texture image synthesis","authors":"Chong-Yung Chi, Chii-Horng Chen","doi":"10.1109/SIPS.1999.822347","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822347","url":null,"abstract":"Shalvi and Weillstein's (1993) 1D computationally efficient super-exponential (SE) algorithm for blind deconvolution is extended to a 2D SE algorithm. Then a noise-insensitive 2D blind system identification (BSI) algorithm using the computationally efficient 2D SE algorithm is proposed for the estimation of 2D linear shift-invariant (LSI) systems. Moreover, a texture synthesis method (TSM) using the proposed BSI algorithm is proposed for texture image synthesis. Finally, some simulation and experimental results are provided to support the efficacy of the proposed BSI algorithm and that of the proposed TSM, respectively.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125838756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Direct implementation of 2-D DCT on a low-cost linear-array architecture without intermediate transpose memory 在低成本线性阵列架构上直接实现二维DCT，无需中间转置存储器
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822314
Shen-Fu Hsiao, Jian-Ming Tseng
{"title":"Direct implementation of 2-D DCT on a low-cost linear-array architecture without intermediate transpose memory","authors":"Shen-Fu Hsiao, Jian-Ming Tseng","doi":"10.1109/SIPS.1999.822314","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822314","url":null,"abstract":"A direct method for the computation of 2-D DCT on a linear-array architecture is presented. The original 2-D DCT is converted into 1-D problem with representation of matrix-vector product. Then, we propose a fast algorithm with low computation complexity, and exploit an efficient mapping technique to generate from the algorithm a hardware-efficient architecture. Unlike other 2-D DCT processors that usually require transpose memory, our new architecture is easily pipelined for purpose of high throughput rate and is easily scalable for the computation of longer-length DCT.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126108376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An improved pyramid algorithm for synthesizing 2-D discrete wavelet transforms 二维离散小波变换合成的改进金字塔算法
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822312
Chu Yu, Sao-Jie Chen
{"title":"An improved pyramid algorithm for synthesizing 2-D discrete wavelet transforms","authors":"Chu Yu, Sao-Jie Chen","doi":"10.1109/SIPS.1999.822312","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822312","url":null,"abstract":"The pyramid algorithm (PA) has been shown very suitable for computing 2-D forward and inverse discrete wavelet transforms (DWT). In this paper, we present a new 2-D synthesis PA to improve some defects encountered in the classical PA algorithm that usually requires large latency, long computation time, and big memory space. Unlike the PA algorithm which computes a 2-D IDWT level by level, our proposed algorithm performs a 2-D DWT in word size. Thus, for processing an N/spl times/N 2-D IDWT with m levels and L-tap filters, the proposed algorithm needs a latency of 3m+4, computes only in N/sup 2/ clock cycles, and spends 2NL+4(m-1) memory space.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":" 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113947090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy issues in multimedia systems 多媒体系统中的能源问题
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822304
M. J. Irwin, V. Narayanan
{"title":"Energy issues in multimedia systems","authors":"M. J. Irwin, V. Narayanan","doi":"10.1109/SIPS.1999.822304","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822304","url":null,"abstract":"This paper presents possible optimization to reduce the energy budget for systems-on-chip (SoC) designs that will be used in next generation multimedia systems. Since future multimedia systems will include the processor core(s), the entire memory system, system buses, I/O controllers, system clocking and control and, in wireless applications, RF components, all on one chip, lowering power dissipation in next generation multimedia chips presents a number of design challenges. Possible strategies for managing the power budget in future multimedia SoCs are presented. Reducing the power consumption of the memory system, system control, and system buses are a particular focus.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130553523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Principle and applications of asymmetric crosstalk-resistant adaptive noise canceller 非对称抗串扰自适应消噪原理及应用
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822367
Sen M. Kuo, W. Peng
{"title":"Principle and applications of asymmetric crosstalk-resistant adaptive noise canceller","authors":"Sen M. Kuo, W. Peng","doi":"10.1109/SIPS.1999.822367","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822367","url":null,"abstract":"This paper analyzes the performance of the crosstalk-resistant adaptive noise canceller (CTRANC). The CTRANC system's symmetric structure causes inconsistent performance when treating noise coming from different incident angles. To solve this problem, an asymmetric CTRANC (ACTRANC) structure using a delay unit on the primary channel is proposed. The ACTRANC allows flexible alignment of the noise source with the sensor array in advanced communication applications such as adaptive noise cancellation, acoustic echo cancellation and adaptive beamforming.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131334885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The TANGRAM co-processor for MPEG-4 visual compositing 用于MPEG-4视觉合成的TANGRAM协处理器
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822336
Mladen Berekovic, T. Selinger, C. Miro, G. Ghigo, C. Heer, P. Pirsch, Kai-Immo Wels, A. Lafage
{"title":"The TANGRAM co-processor for MPEG-4 visual compositing","authors":"Mladen Berekovic, T. Selinger, C. Miro, G. Ghigo, C. Heer, P. Pirsch, Kai-Immo Wels, A. Lafage","doi":"10.1109/SIPS.1999.822336","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822336","url":null,"abstract":"MPEG-4 is the most recent coding standard for multimedia applications. It introduces script-based compositing of audiovisual scenes from multiple audio and visual objects. The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive last stage in the decoding process, which is specific to MPEG-4: rendering and final composition of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 /spl mu/ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm/sup 2/ overall area and 1 Watt power dissipation. The presented TANGRAM co-processor has sufficient performance for rendering of MPEG-4 Main Profile@ Layer3 scenes (CCIR).","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"528 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124497850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low-power CDMA multiuser receiver architectures 低功耗CDMA多用户接收机结构
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822355
Tao Long, Naresh R Shanbhag
{"title":"Low-power CDMA multiuser receiver architectures","authors":"Tao Long, Naresh R Shanbhag","doi":"10.1109/SIPS.1999.822355","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822355","url":null,"abstract":"Presented in this paper are low-power, reconfigurable adaptive CDMA multiuser receiver architectures developed via dynamic algorithmic transforms (DAT). The architectures achieve low-power operation via run-time reconfiguration of receiver complexity to match the requirements of a time-varying multiuser channel. Simulation results with 0.25 /spl mu/m, 2.3 V CMOS technology parameters indicate that the proposed architectures have high resistance to the near-far problem, and can achieve up to 60.4% in power savings compared to architectures without DAT depending on the interference situation.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Performance evaluation of motion estimation algorithms for digital signal processors 数字信号处理器运动估计算法的性能评价
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822308
S. Reader, T. Meng
{"title":"Performance evaluation of motion estimation algorithms for digital signal processors","authors":"S. Reader, T. Meng","doi":"10.1109/SIPS.1999.822308","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822308","url":null,"abstract":"Current implementations of MPEG2 encoders are specially designed in order to perform a huge number of operations, most of which occur during motion estimation. Many fast algorithms have been proposed to reduce the processing power necessary. This paper examines the results achieved by several methods that show promise for reducing computation while sacrificing as little image quality as possible. Methods that achieve these goals are desirable for use in future encoders that will be implemented on generic digital signal processors (DSPs).","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128930570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A compact IDCT processor for HDTV applications 用于高清电视应用的紧凑型IDCT处理器
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822320
Tian-Sheuan Chang, Jiun-In Guo, C. Jen
{"title":"A compact IDCT processor for HDTV applications","authors":"Tian-Sheuan Chang, Jiun-In Guo, C. Jen","doi":"10.1109/SIPS.1999.822320","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822320","url":null,"abstract":"This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100M pixels/sec throughput.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Block-floating-point implementation of recursive computations on a multiple datapath DSP 块浮点递归计算在多数据路径DSP上的实现
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822327
S. Kobayashi, G. Fettweis
{"title":"Block-floating-point implementation of recursive computations on a multiple datapath DSP","authors":"S. Kobayashi, G. Fettweis","doi":"10.1109/SIPS.1999.822327","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822327","url":null,"abstract":"The realization of recursive computation on multiple datapath digital signal processors (DSPs) is studied. A block-floating-point implementation is also proposed. This implementation requires only one guard bit in the accumulator, thus leading to a low complex hardware. This implementation allows a superior signal processing accuracy compared to that of short-word floating-point or fixed-point.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130115437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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