A compact IDCT processor for HDTV applications

Abstract

This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100M pixels/sec throughput.