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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)最新文献

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Implementation of an integer wavelet transform on a parallel TI TMS320C40 platform 整数小波变换在并行TI TMS320C40平台上的实现
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.1999.822313
P. Schelkens, F. Decroos, J. Cornelis, G. Lafruit, F. Catthoor
{"title":"Implementation of an integer wavelet transform on a parallel TI TMS320C40 platform","authors":"P. Schelkens, F. Decroos, J. Cornelis, G. Lafruit, F. Catthoor","doi":"10.1109/SIPS.1999.822313","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822313","url":null,"abstract":"We present the implementation of an integer wavelet transform on a parallel TI TMS320C40-platform. The design space exploration is not driven by arithmetic optimizations, but rather by data transfer and storage estimates. The main focus of this paper lies on the detailed memory organization exploration. A number of implementation approaches is discussed. Based on the memory constraints imposed by the selected platform, the classical row-column approach was selected. By efficiently exploiting the DMA-facilities of the TMS320C40, we have realized a near real-time implementation.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132581297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Streaming video over internet - issues and new development 网络视频流的问题和新发展
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.1999.822303
{"title":"Streaming video over internet - issues and new development","authors":"","doi":"10.1109/SIPS.1999.822303","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822303","url":null,"abstract":"This talk addresses the issues and challenges about streaming video over 1P networks. New techniques on packetization, feedback control, rate-scalable coding, and error concealment are discussed. We put emphasis on specific algorithms that maximize the QoS for streaming MPEG4 video over IP. Issues such as packetization strategies taking advantage of MVO structure, shape alignment, and bistream layering are illustrated. A new end-to-end architecture is proposed for both existing IP infrastructure as well as new generations of IP networks.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133244659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A cost-effective design for MPEG2 audio decoder with embedded RISC core 基于嵌入式RISC内核的MPEG2音频解码器的高性价比设计
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.1999.822341
T. Tsai, Liang-Gee Chen, R. Wu
{"title":"A cost-effective design for MPEG2 audio decoder with embedded RISC core","authors":"T. Tsai, Liang-Gee Chen, R. Wu","doi":"10.1109/SIPS.1999.822341","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822341","url":null,"abstract":"MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. The first type is regular but computation-intensive such as filtering, matrixing, degrouping, and transformation operations. The second type is not regular but computation-intensive such as parsing bitstream, setting operation mode and controlling of all system operations. Based on standard cell design technique, the chip size is 6.4/spl times/6.4 mm/sup 2/, and the tested chip can run at maximum 43.5 MHz clock rate.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132861304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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