{"title":"在低成本线性阵列架构上直接实现二维DCT,无需中间转置存储器","authors":"Shen-Fu Hsiao, Jian-Ming Tseng","doi":"10.1109/SIPS.1999.822314","DOIUrl":null,"url":null,"abstract":"A direct method for the computation of 2-D DCT on a linear-array architecture is presented. The original 2-D DCT is converted into 1-D problem with representation of matrix-vector product. Then, we propose a fast algorithm with low computation complexity, and exploit an efficient mapping technique to generate from the algorithm a hardware-efficient architecture. Unlike other 2-D DCT processors that usually require transpose memory, our new architecture is easily pipelined for purpose of high throughput rate and is easily scalable for the computation of longer-length DCT.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Direct implementation of 2-D DCT on a low-cost linear-array architecture without intermediate transpose memory\",\"authors\":\"Shen-Fu Hsiao, Jian-Ming Tseng\",\"doi\":\"10.1109/SIPS.1999.822314\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A direct method for the computation of 2-D DCT on a linear-array architecture is presented. The original 2-D DCT is converted into 1-D problem with representation of matrix-vector product. Then, we propose a fast algorithm with low computation complexity, and exploit an efficient mapping technique to generate from the algorithm a hardware-efficient architecture. Unlike other 2-D DCT processors that usually require transpose memory, our new architecture is easily pipelined for purpose of high throughput rate and is easily scalable for the computation of longer-length DCT.\",\"PeriodicalId\":275030,\"journal\":{\"name\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.1999.822314\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1999.822314","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Direct implementation of 2-D DCT on a low-cost linear-array architecture without intermediate transpose memory
A direct method for the computation of 2-D DCT on a linear-array architecture is presented. The original 2-D DCT is converted into 1-D problem with representation of matrix-vector product. Then, we propose a fast algorithm with low computation complexity, and exploit an efficient mapping technique to generate from the algorithm a hardware-efficient architecture. Unlike other 2-D DCT processors that usually require transpose memory, our new architecture is easily pipelined for purpose of high throughput rate and is easily scalable for the computation of longer-length DCT.