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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)最新文献

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Architectures for multimedia signal processing 多媒体信号处理体系结构
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822301
P. Pirsch
{"title":"Architectures for multimedia signal processing","authors":"P. Pirsch","doi":"10.1109/SIPS.1999.822301","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822301","url":null,"abstract":"Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It is shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts-reconfigurable computing, simultaneous multithreading, and associative controlling-are presented, and their potential to increase further the performance on future multimedia applications is investigated.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127322227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A co-design based high-performance real-time GIS 基于协同设计的高性能实时GIS
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822346
Wael Badawy, A. Kumar, M. Bayoumi
{"title":"A co-design based high-performance real-time GIS","authors":"Wael Badawy, A. Kumar, M. Bayoumi","doi":"10.1109/SIPS.1999.822346","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822346","url":null,"abstract":"This paper presents a co-design approach for implementing the map overlaying operation for a high-performance real-time geographical information system (GIS). The map overlaying is the most important but also the most computation-intensive operation in GIS systems. Development of an embedded environment for attaining high performance is achieved by implementing a certain computational core in hardware which is efficiently used by software. The methodology partitions the hardware/software parts based on evaluation of a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach results in impressive throughput improvement without sacrificing any flexibility.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fast-rotations based floating point vectoring algorithm 基于快速旋转的浮点矢量算法
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822328
K. van der Kolk, J. lee, E. Deprettere
{"title":"A fast-rotations based floating point vectoring algorithm","authors":"K. van der Kolk, J. lee, E. Deprettere","doi":"10.1109/SIPS.1999.822328","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822328","url":null,"abstract":"The idea of approximate rotations has been introduced by J. Gotze and G. Hekstra. G Hekstra and E. Deprettere extended the concept to orthogonal fast rotations and formalized the concept by providing a fast rotation theory. In this theory, the emphasis has been on fast rotation, whereas fast rotation-based vectorization has only been considered in an approximating sense in examples published by J. Gotze and G. Hekstra. The formalization of fast rotation-based vectorization is the subject of this paper. The few known approximate fast vectorization algorithms are special cases of the generic fast rotation-based vectorization algorithm proposed in this paper.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128239693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme 基于位串行方案的高吞吐率、低电路复杂度的QAM信道均衡器设计
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822362
Y. Hwang, Wei-Cheng Lin
{"title":"A high throughput rate and low circuit complexity QAM channel equalizer design based on bit serial scheme","authors":"Y. Hwang, Wei-Cheng Lin","doi":"10.1109/SIPS.1999.822362","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822362","url":null,"abstract":"In this paper, a novel VLSI design for an all digital QAM channel equalizer is presented. We adopted a decision-feedback equalizer (DFE) structure to combat the inter-symbol-interference (ISI) induced during high speed data communication. The equalizer consists mainly of eight transversal adaptive filters and slicers. Since the adaptive filter along with the slicer will form a nonlinear feedback path, the resultant recursive computing often leads to a severe performance bottleneck. To overcome this, a bit serial, MSB first computing scheme based on distributed arithmetic and signed digit number system techniques was developed. In our scheme, the next symbol's equalization can be started as soon as the MSD of the current symbol is obtained. This leads to a computation overlap between successive symbol's equalization and can effectively improve the baud rate. The circuit complexity, however, is still kept low with the help of fine grain pipelining. With careful arrangement of data flow, an efficient systolic array design with 100% utilization and suitable for VLSI implementation is derived. The design architecture is also scalable in that the initiation interval between the processing of two consecutive symbols is a constant of 5+[m/4] clocks (in the delayed sign LMS case) and the hardware complexity is of order 2/spl middot/m/spl middot/(n+1), where m and n are tap order and word length.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131011120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
NEDA: a new distributed arithmetic architecture and its application to one dimensional discrete cosine transform NEDA:一种新的分布式算法架构及其在一维离散余弦变换中的应用
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822321
W. Pan, A. Shams, M. Bayoumi
{"title":"NEDA: a new distributed arithmetic architecture and its application to one dimensional discrete cosine transform","authors":"W. Pan, A. Shams, M. Bayoumi","doi":"10.1109/SIPS.1999.822321","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822321","url":null,"abstract":"Conventional Distributed Arithmetic (DA) is popular in ASIC design and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in Digital Signal Processing (DSP) applications. Mathematical analysis proves that NEDA can implement inner product of vectors in the form of 2's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative study shows that NEDA outperforms widely-used approaches such as MAC and DA in many aspects. Being a high speed architecture free of ROM, multiplication and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architecture for one dimensional DCT core is presented as an example.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124204006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Enhanced DSP core for embedded applications 增强的DSP核心用于嵌入式应用
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822332
J. Takala, M. Kuulusa, P. Ojala, J. Nurmi
{"title":"Enhanced DSP core for embedded applications","authors":"J. Takala, M. Kuulusa, P. Ojala, J. Nurmi","doi":"10.1109/SIPS.1999.822332","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822332","url":null,"abstract":"This paper describes a set of enhancements that were implemented to a 16-bit DSP core. The added features include several instructions, extended program/data address spaces, vectored interrupts, and improved low-power operation. Embedded system development flow was reinforced with an optimizing C-compiler and a compact real-time operating system.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128849715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new network processor architecture for high-speed communications 一种用于高速通信的新型网络处理器架构
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822361
Xiaoning Nie, Lajos Gazsi, F. Engel, Gerhard Fettweis
{"title":"A new network processor architecture for high-speed communications","authors":"Xiaoning Nie, Lajos Gazsi, F. Engel, Gerhard Fettweis","doi":"10.1109/SIPS.1999.822361","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822361","url":null,"abstract":"Many applications require high-speed communications. To provide protocol processing with efficient hardware and software the use of a flexible and efficient platform becomes very important for high-speed communications networks. In this paper we first describe a top-level view of the implementations platform for handling communication protocols. From the top-level view we derived the requirements on a network processor (NP) which will be particularly useful for high-speed communications devices. To this end an efficient NP architecture is designed and implemented to meet the requirements. The key features of such a NP are bit field instructions, port-based instructions and the zero-latency task switch among others.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128960255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
A novel hardware algorithm for residue evaluation 一种新的残差评估硬件算法
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822374
K. Karagianni, T. Stouraitis
{"title":"A novel hardware algorithm for residue evaluation","authors":"K. Karagianni, T. Stouraitis","doi":"10.1109/SIPS.1999.822374","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822374","url":null,"abstract":"An efficient hardware algorithm for the conversion of an integer X to its residue module a predefined integer m, is introduced. The algorithm is based on successive subtractions of appropriately selected multiples of m, from the input X, and it leads to fast evaluation of the residue, via hardware of low complexity. A VLSI architecture for the implementation of the algorithm is also proposed.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131889580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Gabor filter-based approach to fingerprint recognition 基于Gabor滤波器的指纹识别方法
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822342
Chih-Jen Lee, Sheng-De Wang
{"title":"A Gabor filter-based approach to fingerprint recognition","authors":"Chih-Jen Lee, Sheng-De Wang","doi":"10.1109/SIPS.1999.822342","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822342","url":null,"abstract":"We propose a Gabor-filter-based method for fingerprint recognition in this paper. The method makes use of Gabor filtering technologies and need only to do the core point detection before the feature extraction process without any other pre-processing steps such as smoothing, binarization, thinning, and minutiae detection. The proposed Gabor-filter-based features play a central role in the processes of fingerprint recognition, including local ridge orientation, core point detection, and feature extraction. Experimental results show that the recognition rate of the k-nearest neighbor classifier using the proposed features is 97.2% for a small-scale fingerprint database, and thus that the proposed method is an efficient and reliable approach.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124879044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Power reduction in wireless receivers through multistage digital filtering and quantization 通过多级数字滤波和量化降低无线接收机的功率
1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI: 10.1109/SIPS.1999.822358
J. Andrews, T. Meng
{"title":"Power reduction in wireless receivers through multistage digital filtering and quantization","authors":"J. Andrews, T. Meng","doi":"10.1109/SIPS.1999.822358","DOIUrl":"https://doi.org/10.1109/SIPS.1999.822358","url":null,"abstract":"The number of bits required to accurately represent a received signal in a wireless system changes as the out-of-band interference is removed by an IIR digital filter, if the filtering is done in stages, such as second-order sections. Taking advantage of this fact can reduce the size of the datapath in a VLSI realization of a digital filter, and hence power and area can be saved without decreasing performance. An effective algorithm for computing this reduced number of bits to use for quantization after each stage is derived, and a scheme for optimally ordering the second-order sections is presented, power savings range from 33% to 50%, depending on the amount of out-of-band interference.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122039622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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