{"title":"增强的DSP核心用于嵌入式应用","authors":"J. Takala, M. Kuulusa, P. Ojala, J. Nurmi","doi":"10.1109/SIPS.1999.822332","DOIUrl":null,"url":null,"abstract":"This paper describes a set of enhancements that were implemented to a 16-bit DSP core. The added features include several instructions, extended program/data address spaces, vectored interrupts, and improved low-power operation. Embedded system development flow was reinforced with an optimizing C-compiler and a compact real-time operating system.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Enhanced DSP core for embedded applications\",\"authors\":\"J. Takala, M. Kuulusa, P. Ojala, J. Nurmi\",\"doi\":\"10.1109/SIPS.1999.822332\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a set of enhancements that were implemented to a 16-bit DSP core. The added features include several instructions, extended program/data address spaces, vectored interrupts, and improved low-power operation. Embedded system development flow was reinforced with an optimizing C-compiler and a compact real-time operating system.\",\"PeriodicalId\":275030,\"journal\":{\"name\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.1999.822332\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1999.822332","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes a set of enhancements that were implemented to a 16-bit DSP core. The added features include several instructions, extended program/data address spaces, vectored interrupts, and improved low-power operation. Embedded system development flow was reinforced with an optimizing C-compiler and a compact real-time operating system.