{"title":"基于协同设计的高性能实时GIS","authors":"Wael Badawy, A. Kumar, M. Bayoumi","doi":"10.1109/SIPS.1999.822346","DOIUrl":null,"url":null,"abstract":"This paper presents a co-design approach for implementing the map overlaying operation for a high-performance real-time geographical information system (GIS). The map overlaying is the most important but also the most computation-intensive operation in GIS systems. Development of an embedded environment for attaining high performance is achieved by implementing a certain computational core in hardware which is efficiently used by software. The methodology partitions the hardware/software parts based on evaluation of a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach results in impressive throughput improvement without sacrificing any flexibility.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A co-design based high-performance real-time GIS\",\"authors\":\"Wael Badawy, A. Kumar, M. Bayoumi\",\"doi\":\"10.1109/SIPS.1999.822346\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a co-design approach for implementing the map overlaying operation for a high-performance real-time geographical information system (GIS). The map overlaying is the most important but also the most computation-intensive operation in GIS systems. Development of an embedded environment for attaining high performance is achieved by implementing a certain computational core in hardware which is efficiently used by software. The methodology partitions the hardware/software parts based on evaluation of a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach results in impressive throughput improvement without sacrificing any flexibility.\",\"PeriodicalId\":275030,\"journal\":{\"name\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.1999.822346\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1999.822346","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a co-design approach for implementing the map overlaying operation for a high-performance real-time geographical information system (GIS). The map overlaying is the most important but also the most computation-intensive operation in GIS systems. Development of an embedded environment for attaining high performance is achieved by implementing a certain computational core in hardware which is efficiently used by software. The methodology partitions the hardware/software parts based on evaluation of a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach results in impressive throughput improvement without sacrificing any flexibility.