H. Pandey, M. Shaygan, S. Sawallich, S. Kataria, M. Otto, Zhenxing Wang, M. Nagel, D. Neumaier, M. Lemme
{"title":"All CVD Boron Nitride Encapsulated Graphene FETs","authors":"H. Pandey, M. Shaygan, S. Sawallich, S. Kataria, M. Otto, Zhenxing Wang, M. Nagel, D. Neumaier, M. Lemme","doi":"10.1109/DRC.2018.8442264","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442264","url":null,"abstract":"Graphene is at the forefront of 2D material research, with many reports demonstrating the possibility of large area growth by means of chemical vapor deposition (CVD) [1]–[3]. Boron Nitride (BN) has been suggested to be the favorable substrate and encapsulation material for graphene devices as it preserves the intrinsic mobility performance [4]–[6]. However, the demonstration of BN-encapsulated graphene field effect transistors (GFETs) is so far limited to devices made from manually exfoliated flakes. Here, we report on CVD grown GFETs encapsulated by CVD grown BN with CMOS compatible nickel (Ni) edge contacts to the channel and discuss their performance.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Epitaxial Gd2O3on Si (111) Substrate by Sputtering to Enable Low Cost SOI","authors":"K. R. K. Amlta, A. Laha, S. Mahapatra, U. Gangway","doi":"10.1109/DRC.2018.8442170","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442170","url":null,"abstract":"Silicon on insulator (SOI) enables RF technology at advanced nodes [1]. The SOI-wafer cost is the key challenge due to complex manufacturing processes such as “smart cut” or wafer bonding [2]. The epitaxial growth of rare earth (RE) oxides followed by epi-Si growth is extensively explored for SOI stack preparation. Low lattice mismatch (~0.5%) between Si and RE oxides such as Ce<inf>2</inf>O<inf>3</inf>, Pr<inf>2</inf>0<inf>3</inf>, Gd<inf>2</inf>0<inf>3</inf> etc. [3], make it suitable for isolation oxide (IO) for SOI. Among all, Gd<inf>2</inf>0<inf>3</inf> is proven most promising, due to stable oxidation state (+3) [3], large band gap (~5.9 eV) and, sufficient band offset <tex>$(Delta mathrm{E}_{mathrm{c}}=2.1mathrm{eV}&Delta mathrm{E}_{mathrm{v}}=2.8mathrm{eV})$</tex> [4]. Epi-Gd<inf>2</inf>0<inf>3</inf> has potential to be an attractive alternative for gate dielectric and IO layer [5]–[8] in advanced CMOS technology.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"81 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116339963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A unified current-voltage and charge-voltage model of quasi-ballistic III-nitride HEMTs for RF applications","authors":"Kexin Li, S. Rakheja","doi":"10.1109/DRC.2018.8442193","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442193","url":null,"abstract":"III-nitride high electron mobility transistors (HEMTs) are a strong candidate for high-power radio frequency (RF) applications due to their ability to support high breakdown fields, while maintaining a high electron mobility and a high density of the two-dimensional electron gas (2DEG). Analytic device models that are physically motivated and mathematically robust are preferred for circuit simulations. Most prior works have focused on compact models for 111-nitride HEMTs that operate in the drift-diffusive limit, while Ref. [1] presents a threshold-voltage-based compact model for quasi-ballistic gallium nitride (GaN) HEMTs using an empirical channel charge model. In this paper, we present a unified and self-consistent current-voltage (I-V) and capacitance-voltage (C-V) model of III-nitride HEMTs that is valid for quasi-ballistic transport. The terminal charges are used to calculate inter-nodal capacitances ensuring charge conservation in the device. Both I-V and C-V model are validated against numerical TCAD simulations and experimental data of short-channel GaN HEMTs. Effects of fringing charge resulting from bulk and surface traps are also incorporated in the model. Key equations of the dynamic model are presented in Table 1. Details of the static I-V model of III-nitride HEMTs are presented elsewhere by the authors [2], and equations are omitted for brevity.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124515257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Peimyoo, J. Mehew, M. Barnes, A. D. Sanctis, I. Amit, J. Escolar, K. Anastasiou, Ali Gholina, A. Rooney, S. Haigh, S. Russo, M. Craciun, F. Withers
{"title":"Photo-oxidized HfS2 - An embeddable and writable high-k dielectric for flexible Van der Waals nano-electronics","authors":"N. Peimyoo, J. Mehew, M. Barnes, A. D. Sanctis, I. Amit, J. Escolar, K. Anastasiou, Ali Gholina, A. Rooney, S. Haigh, S. Russo, M. Craciun, F. Withers","doi":"10.1109/DRC.2018.8442164","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442164","url":null,"abstract":"Scaling improvements in conventional semiconductor devices have been facilitated by incorporating high-k dielectric materials such as Hf02[1]. This has led to increased device density and lower drive voltages. Similarly, the rapid technological progress of flexible Van der Waals (VdW) heterostructure devices based on two-dimensional (2D) materials, will also likely require comparable scaling to reduce device drive voltages to a comparable level (~ 1 V). Typically, flexible VdW heterostructures rely on high purity hexagonal boron nitride dielectrics (hBN) which has a dielectric constant $ksim 4$, 4-5 times smaller than Hf02[2]. To overcome these limitations, we developed a novel technology to incorporate the high-k dielectric HfOx within VdW heterostructures through photo-oxidation of the 2D semiconductor HfS2 via laser irradiation. The resultant oxide is found to have a dielectric constant $ksim 15$. This oxide can be selectively written even once embedded within complex multi-layer VdW heterostructures, and under metallic contacts. This avoids the need for expensive sputtering and atomic layer deposition techniques, which are known to badly damage 2D materials. We exploit this technology to demonstrate several different VdW devices to suit various functionalities, including: flexible field effect transistors (FETs), resistive switching memory elements (ReRAMs) and light emitting and ultra-fast light detecting quantum well structures. All these devices show performances equal or superior to state-of-the-art VdW devices, with FETs displaying on/off ratios of 104 and subthreshold swings of 60 mV / dec.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124572999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"First demonstration of vacuum-sealed fully integrated BEOL-compatible field emission devices for Si integrated high voltage applications","authors":"N. Deka, V. Subramanian","doi":"10.1109/DRC.2018.8442219","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442219","url":null,"abstract":"CMOS-integrated high voltage devices are needed for applications in sensors / actuators and power systems. Current high voltage technologies based on GaN and SiC are not easily integrated with silicon CMOS [1]–[2]. Vacuum nanoelectronic devices based on field emission are a promising alternative approach for achieving high voltage devices on Si. Because vacuum serves as the electron transport medium, the blocking voltages in these devices can be much higher than their solid-state counterparts [3]. To date, however, there have been very few reports of fully integrated field emitters, most of which require high vacuum operation, are not CMOS-compatible and demonstrate poor scalability [4]–[6]. Here, we demonstrate the first vacuum-sealed fully integrated diode and triode field emission arrays that are developed in a scalable, BEOL-compatible process directly on Si. We extensively characterize both diode and triode arrays, demonstrating gate modulated field emission in the on-state and blocking voltages of200V.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121071857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Rai, J. Park, Chenxi Zhang, I. Kwak, S. Wolf, S. Vishwanath, Xinyu Lin, J. Furdyna, H. Xing, Kyeongjae Cho, A. Kummel, S. Banerjee
{"title":"Enhanced P-Type Behavior in 2D WSe2 via Chemical Defect Engineering","authors":"A. Rai, J. Park, Chenxi Zhang, I. Kwak, S. Wolf, S. Vishwanath, Xinyu Lin, J. Furdyna, H. Xing, Kyeongjae Cho, A. Kummel, S. Banerjee","doi":"10.1109/DRC.2018.8442266","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442266","url":null,"abstract":"Defect engineering of2D semiconducting transition metal dichalcogenides (TMDCs) has been demonstrated to be a promising way to tune both their bandgaps and carrier concentrations. Moreover, controlled introduction of defects in the source/drain access regions of a TMDC FET can boost its performance by decreasing the contact resistance at the metallTMDC interface [1]. While chemical functionalization offers a facile route towards defect engineering in 2D TMDCs, several chemically-treated TMDCs have not been fully understood at the molecular level. In this study, chemical sulfur treatment (ST) utilizing ammonium sulfide [(NH4)2S] solution is shown to enhance the p-type behavior in 2D WSe2 via introduction of acceptor defect states near its valence band edge (VBE), with the results verified using detailed scanning tunneling microscopy (STM)/spectroscopy (STS) studies, field-effect transistor (FET) measurements and theoretical density-of-states (DOS) calculations.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122406333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Songtao Liu, J. Norman, D. Jung, M. Kennedy, A. Gossard, J. Bowers
{"title":"9 GHz passively mode locked quantum dot lasers directly grown on Si","authors":"Songtao Liu, J. Norman, D. Jung, M. Kennedy, A. Gossard, J. Bowers","doi":"10.1109/DRC.2018.8442165","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442165","url":null,"abstract":"Photonics is born to help overcome the copper wires physical limits to transmit data at higher speed","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125505119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. A. Heidarlou, B. Jariwala, P. Paletti, S. Rouvimov, J. A. Robinsorr, S. Fullerton‐Shirey, A. Seabaugh
{"title":"Supercapacity (>1000 fJF/cm2) charge release in a CVD-grown WSe2 FET incorporating a PEO: CsCI04 side gate","authors":"M. A. Heidarlou, B. Jariwala, P. Paletti, S. Rouvimov, J. A. Robinsorr, S. Fullerton‐Shirey, A. Seabaugh","doi":"10.1109/DRC.2018.8442277","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442277","url":null,"abstract":"We report extraordinarily high capacitance density in tungsten diselenide (WSe2) field-effect transistors (FETs) capped with polyethylene oxide (PEO) and ion doped with cesium perchlorate (CsCI04). The FETs have 3–4 monolayer WSe2 channels grown by chemical vapor deposition (CVD) using W(CO)6 and H2Se at 800 °C for 30 minutes [1]. A stepper-based process was used to fabricate the transistors and an 11 nm Al2O3 atomic layer deposited (ALD) gate dielectric was formed on the WSe2 with a low temperature nucleation layer, 1 nm Ah03, deposited at 110 °C to facilitate nucleation followed by a 10 nm Ah03 deposited at 200 °C, after Kwak [2]. The n-FET achieves an ON/OFF ratio of 106 with noise-floor-limited gate current. Most prior studies of WSe2 FETs have been on exfoliated materials and to our knowledge there is only one prior report of a top-gated CVD WSe2 p-FET [3]. Following FET characterization PEO: CsCI04 was drop-cast and annealed at 90 °C for 3 minutes in Ar after Xu [4], yielding a layer thickness of 400 nm as measured by transmission electron microscopy (TEM). Ion gating using a side gate ($6 mumathrm{m}$ from the WSe2 mesa edge) produces ambipolar transfer characteristics with approximately equal ON-currents of $2 mumathrm{A}/mumathrm{m}$ attributed to the multi-work-function source/drain contacts [5]. ON/OFF current ratio exceeds 106 with field-effect electron and hole mobilities of 10 and 25 cm2/Vs respectively and subthreshold swings of 260 and 180 mY/decade respectively. Atomic force microscope images show that the WSe2 nucleates in triangles which are apparent in Fig. 1; FET characteristics after testing of the transistor are shown in Fig. 2 along with TEM.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121712409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-level 2-bit/cell operation utilizing Hf-based MONOS nonvolatile memory","authors":"S. Kudoh, S. Ohmi","doi":"10.1109/DRC.2018.8442216","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442216","url":null,"abstract":"Metal-oxide-nitride-oxide-silicon (MONOS) type memory is a promising candidate to replace the conventional floating-gate (FG) type nonvolatile memory (NVM) [1]. Furthermore, the multi-level 2-bit/cell operation is necessary to realize for the high integration flash memory [2]. We have reported the excellent electrical characteristics of fully in-situ formed Hf-based MONOS NVM, which was able to be injected electron from sourceldrain region when NVM was operated by 6 V/2 ms [3]–[5]. In this study, multi-level 2-bit/cell operation of Hf-based MONOS NVM was investigated.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129014717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}