{"title":"Tunable Random Number Generation Using Single Superparamagnet with Perpendicular Magnetic Anisotropy","authors":"Punyashloka Debashis, Zhihong Chen","doi":"10.1109/DRC.2018.8442154","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442154","url":null,"abstract":"Hardware random number generators (RNGs) are specialized circuits that often come with large silicon footprints1. In this work, we experimentally demonstrate a RNG using a single low barrier magnet with perpendicular magnetic anisotropy (PMA) by utilizing its inherent stochasticity. More importantly, we show the tunability of its randomness by applying magnetic field or current, which makes this device an ideal candidate for probabilistic cormutinu-.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Three-Terminal Edge-Triggered Mott Switch","authors":"A. Aziz, R. Engel-Herbert, S. Gupta, N. Shukla","doi":"10.1109/DRC.2018.8442274","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442274","url":null,"abstract":"We demonstrate a novel $mathrm{VO}_{2}-mathrm{based}$ edge-triggered (ET) three-terminal Mott switch that leverages the displacement current induced by the switching of the gate voltage pulse to trigger an IMT in the $mathrm{VO}_{2}$ channel. The design overcomes a long-standing challenge of realizing a three-terminal $mathrm{VO}_{2}$ switch due to the absence of field-effect induced IMT in VO2. The ET Mott switch also enables isolation between the input & the output (at steady state), and facilitates reduction in the effective trigger voltage in comparison to the two-terminal configuration. We show using simulations that these properties can be exploited to enable a BEOL-compatible 3T selector for MTJ-based cross-point memory, showing $3.4times$ higher cell TMR, as well as 45% & 40% lower sneak-path current & power, respectively.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122146444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Niharika Thakuria, Daniel S. Schulman, Saptarshi Das, S. Gupta
{"title":"2- Transistor Schmitt Trigger based on 2D Electrostrictive Field Effect Transistors","authors":"Niharika Thakuria, Daniel S. Schulman, Saptarshi Das, S. Gupta","doi":"10.1109/DRC.2018.8442149","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442149","url":null,"abstract":"The 2D Electrostrictive FET (2D EFET) is a steep switching device that operates on the principle of dynamic bandgap (Eo) modulation of 2D channel enabled by voltage induced strain transduction [1]. However, the steep switching comes with its own overheads such as increased capacitance. Further, 2D-EFETs offer distinct features, such as a back terminal with unique control of device characteristics. To overcome the limitations of 2D EFETs, their unique behavior needs to be judiciously capitalized. In this work, we propose a 2-Transistor Schmitt Trigger (ST) based on 2D-EFETs utilizing the dynamic $E_{G}$ reduction and the resultant drive strength modulation driven by $V_{B}$. (Fig. 1). We show the significance of circuit-driven device optimization to enable 2D-EFET based ST employing just two transistors.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications","authors":"S. Thirumala, S. Gupta","doi":"10.1109/DRC.2018.8442186","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442186","url":null,"abstract":"Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of steep switching and non-volatile (NV) transistors [1]. FEFETs may be realized either: (i) with an internal metal layer (w-IML) between ferroelectric (FE e.g. HZO) and dielectric (DE) or (ii) direct integration of FE on DE without the use of internal metal (w/o-IML). Each of these devices have their own issues [2], [3]. FEFETs w/o-IML may be affected by defects in HZO (resulting in trapping/de-trapping [2]), and non-uniform FE electric fields (due to the underlying FET), which may lead to performance degradation/variability [4]. On the other hand, in FEFETs w-IML, the IML is floating and the gate leakage (GL) can result in several issues. The effect of GL in the context of steep switching of FEFETs has been discussed in [3]. Similarly, there is a need to understand the impact of GL in NV FEFETs. In this paper, we analyze the implications of gate leakage in NV FEFETs w-IML and describe how distinguishability between the two NV states can be lost due to GL. We propose gate workfunction (GWF) engineering along with a modified read scheme for FEFET based memory to counter the effect of GL.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128965680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Tossoun, G. Kurczveil, Chong Zhang, D. Liang, R. Beausoleil
{"title":"High-speed 1310 nm Hybrid Silicon Quantum Dot Photodiodes with Ultra-low Dark Current","authors":"B. Tossoun, G. Kurczveil, Chong Zhang, D. Liang, R. Beausoleil","doi":"10.1109/DRC.2018.8442178","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442178","url":null,"abstract":"Development of cost-effective integrated photonics with high-volume manufacturability is necessary for high-speed interconnects in next-generation high-performance computing and fiber-optic communications systems [1]. Silicon photonics can naturally leverage the existing technology infrastructure behind the silicon (Si) complementary metal-oxide semiconductor (CMOS) industry, and has emerged as a new integrated photonic platform in the past decade.). Most silicon PICs typically contain Ge-on-Si photodiodes (PDs) for photodetection in 1310 nm and 1550 nm windows. However, these PDs often suffer from relatively high dark current and high dislocation densities in comparison to alternatives made from III-V semiconductor materials. They also require selective area growth if integrated on the same wafer as lasers made from different materials, complicating the fabrication process and increasing cost. One solution to this is to use the same epitaxial layers for the lasers and the photodiodes. In this paper, we report the first quantum dot (QD) photodiodes heterogeneously integrated on a silicon substrate with record low dark currents (0.01 nA) and record high 3-dB bandwidths (15 GHz), decent responsivity of 0.34 A/W at −9 V, and open eye diagrams up to 12.5 Gb/s. The PD is made using the same epitaxial layers and fabrication process for a recent 1310 nm hybrid QD silicon comb laser with error-free operation for 14-channels [2].","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125579656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yihao Fang, Jonathan P. Sculley, M. Urteaga, A. Carter, P. Yoder, M. Rodwell
{"title":"Design of InP Segmented-collector DHBTs with Reduced Collector Transit Time τc for Large Power Bandwidth Power Amplifiers","authors":"Yihao Fang, Jonathan P. Sculley, M. Urteaga, A. Carter, P. Yoder, M. Rodwell","doi":"10.1109/DRC.2018.8442142","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442142","url":null,"abstract":"InP double-heterojunction bipolar transistors (DHBTs) have demonstrated power gain cutoff frequencies $(f_{max})$ above 1THz under low collector voltage due to electron velocity overshoot in the InP drift collector [1] [2]. Under higher collector voltage, however, a quick onset of $Gamma-mathrm{L}$ scattering limits the average electron velocity to the saturation velocity (Fig. 1(a)-(c)), leading to a Johnson's figure-of-merit (JFOM) second to GaN HEMTs and a limited transistor power bandwidth for InP DHBTs [3]. Here we propose a velocity-engineered device structure called the segmented-collector DHBT (SC-DHBT) that incorporates p-type scattering layers within the drift collector to reduce the electron kinetic energy and force a greater electron distribution into the low effective mass $Gamma-$ valley for extended velocity overshoot (Fig. 3(a)). Transport simulations show the collector transit time $tau_{c}$ is reduced from 1.23ps in the reference design to 0.90ps in a double scatterer design at $V_{cb}=5mathrm{V}, J_{c}{=}$ 1mA/um2. The proposed SC-DHBT design is suited for large power bandwidth power amplifiers.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127724139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Hellenbrand, E. Memišević, J. Svensson, A. Krishnaraja, E. Lind, L. Wernersson
{"title":"Effect of Gate Oxide Defects on Tunnel Transistor RF Performance","authors":"M. Hellenbrand, E. Memišević, J. Svensson, A. Krishnaraja, E. Lind, L. Wernersson","doi":"10.1109/DRC.2018.8442145","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442145","url":null,"abstract":"Tunnel field-effect transistors (TFETs) are designed for low off-state leakage and low drive voltages. To investigate how capable TFETs are of RF operation, we measured their scattering parameters and performed small-signal modeling. We find that in the low frequency ranges, gate oxide defects have a major influence on the RF performance of these devices, which can be modeled by a frequency-dependent gate-to-drain conductance $g_{gd,omega}$. This model is based on charge trapping in gate oxide defects and was studied before for metal-oxide-semiconductor capacitors [1].","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jorge A. Cardenas, Sophia Upshaw, Matthew J. Catenaccr, B. Wiley, A. Franklin
{"title":"Exploring Silver Contact Morphologies in Printed Carbon Nanotube Thin-Film Transistors","authors":"Jorge A. Cardenas, Sophia Upshaw, Matthew J. Catenaccr, B. Wiley, A. Franklin","doi":"10.1109/DRC.2018.8442217","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442217","url":null,"abstract":"Demand for ubiquitous and flexible electronics to facilitate the rapid growth of Internet- of- Things (IoT) technologies has driven the advancement of printed electronics for low-cost and high-throughput manufacturing. The carbon nanotube thin-film transistor (CNT-TFT) is one of the most promising options for printed electronics due to its mechanical flexibility, compatibility with low-temperature fabrication, and relatively high mobility [1]. Meanwhile, Ag nanoparticles remain the most widely used conductive material in printed inks due to their superb dispersion stability, high conductivity, and relatively low cost [2]. However, limited studies have explored the impact of different printed metallic contacts in CNT-TFTs [3], even though the contact interfaces are one of the leading factors limiting performance. In this work, the impact of Ag contact morphology is studied for the first time by fabricating hundreds of CNT-TFTs using an aerosol jet printer to systematically investigate three morphologies (nanoparticle (NP), nanoflake (NF), and nanowire (NW), as seen in Fig. 1) and their impact on device performance. Using what is learned from the contact morphology results, the first CNT-TFTs printed without removal of the substrate from the printer (full “print-in-place” additive devices) are also demonstrated.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134048971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Xiong, Fuu-Jiun Hwang, D. Mao, Geng-Lin Li, Guangyu Xu
{"title":"Color-Filtered Si Photodiode Array for On-Chip Calcium Imaging in Living Cells","authors":"Z. Xiong, Fuu-Jiun Hwang, D. Mao, Geng-Lin Li, Guangyu Xu","doi":"10.1109/DRC.2018.8442212","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442212","url":null,"abstract":"Intracellular calcium dynamics is crucial in understanding cell activities [1]. To monitor the change in intracellular calcium concentration ([Ca2+]), fluorescent imaging has been broadly used for its outstanding sensitivity and specificity [2]. This method delivers fluorescent molecules into living cells. These molecules specifically respond to the binding of Ca2+ ions, followed by a change in their fluorescence intensity. To date, most Ca2+ imaging is conducted by fluorescent microscopes that have high spatiotemporal resolutions. However, these microscopes are usually large in size, and have limited access to cells deep in the tissue [3]. For these reasons, on-chip fluorescent imaging systems have recently emerged as a viable alternative for their miniaturized and implantable nature that can grant deep tissue imaging [4]. In this work, we present an on-chip calcium imaging platform based on a $20-mumathrm{m}$ pitched passive Si photodiode (PD) array assembled with a high-performance color filter. We chose a passive Si PD array structure for their CMOS compatibility and low-power operation (sub- $10 mumathrm{W}$ power, $sim 0.2 mathrm{mW}/mathrm{mm}^{2}$ power density), which allows chronic deep tissue imaging. Importantly, we coated a light absorber layer on top of the PD array to serve as a color filter, which offers $mathrm{a} > 10^{2}$ extinction ratio to reject the excitation light provided by the microscope. The emission light (peaked at ~602 nm) from the calcium indicators in C2C12 cells passes the filter with a > 76% transmission coefficient. The Ca2+ imaging data of our PD array well match with those of a fluorescent microscope. Our results show that calcium ionophores induce heterogeneous intracellular [Ca2+] dynamics in different cells. This work suggests the possible use of the PD array towards an on-chip live-cell imaging system with deep tissue access.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. McClellan, E. Yalon, Lili Cai, S. Suryavanshi, Xiaolin Zheng, E. Pop
{"title":"Sub-Thermionic Steep Switching in Hole-Doped WSe2 Transistors","authors":"C. McClellan, E. Yalon, Lili Cai, S. Suryavanshi, Xiaolin Zheng, E. Pop","doi":"10.1109/DRC.2018.8442237","DOIUrl":"https://doi.org/10.1109/DRC.2018.8442237","url":null,"abstract":"Decreasing the subthreshold swing (SS) of field-effect transistors (FETs) to sub-60 mV/decade at room temperature can enable next-generation low-power electronics [1]. Here, we demonstrate steep switching $(SS < 5mathrm{mV}/mathrm{decade})$ and high on-current $(I_{mathrm{ON}}approx 400mu mathrm{A}/mu mathrm{m})$ in non-uniformly hole-doped WSe2 transistors. By setting up large lateral electric field gradients through spatial variation of doping, we deduce that the abrupt switching behavior is consistent with avalanche (impact ionization [2]) of charge carriers, opening up a new approach to achieve low-power transistors based on ultra-thin 2D materials.","PeriodicalId":269641,"journal":{"name":"2018 76th Device Research Conference (DRC)","volume":"62 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}