Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test最新文献_第4页

Characterization and compensation of performance variability using on-chip monitors 用片上监视器表征和补偿性能变化

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834934

Islam A. K. M. Mahfuzul, H. Onodera

引用次数: 8

A novel abstraction-guided simulation approach using posterior probabilities for verification 一种新颖的抽象引导仿真方法，使用后验概率进行验证

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834864

Jian Wang, Huawei Li, Xiaowei Li

引用次数: 0

Accelerated domain decomposition FEM-BEM solver for magnetic resonance imaging (MRI) via discrete empirical interpolation method 基于离散经验插值法的磁共振成像加速域分解FEM-BEM求解器

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834885

N. Farnoosh, A. Polimeridis, T. Klemas, L. Daniel

{"title":"Accelerated domain decomposition FEM-BEM solver for magnetic resonance imaging (MRI) via discrete empirical interpolation method","authors":"N. Farnoosh, A. Polimeridis, T. Klemas, L. Daniel","doi":"10.1109/VLSI-DAT.2014.6834885","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834885","url":null,"abstract":"A finite element and combined field integral equation domain decomposition approach is presented for electromagnetic scattering from multiple domains. The main computational bottleneck is the construction of the dense coupling impedance matrix blocks capturing the interactions between different domains. In order to accelerate such coupling computation, A. Hochman et al. in [1] proposed the combination of the randomized singular value decomposition (rSVD) and of the discrete empirical interpolation method (DEIM). The computation of the incident fields due to equivalent currents on each domain is reduced to just a few observation points that can be located optimally and automatically by the DEIM algorithm. Furthermore, the compressed form of the coupling blocks generated by that approach significantly reduces the memory requirement and computational cost associated with the iterative solution of the global system matrix. In this paper, we focus on developing an implementation of such approach for a domain decomposition solver that combines finite element method (FEM) with boundary element method (BEM). Results on a simplified magnetic resonance imaging (MRI) scattering on human body are finally presented to validate our code implementation.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"37 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125733147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Output selection for test response compaction based on multiple counters 基于多个计数器的测试响应压缩输出选择

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834865

Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh

引用次数: 3

A dual-mode CMOS image sensor for optical wireless communication 用于光无线通信的双模CMOS图像传感器

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834892

Chih-Hao Lin, C. Hsieh, Che-Chun Lin, Ren-Jr Chen

引用次数: 2

Design of low-cost elliptic curve cryptographic engines for ubiquitous security 低成本椭圆曲线密码引擎的设计

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834883

Hsin-Yu Ting, Chih-Tsun Huang

引用次数: 4

A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils 一种利用电感增强耦合键合线线圈的无源供电谐振抑制滤波器

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834894

Taisuke Hayashi, N. Miura, K. Yoshikawa, M. Nagata

引用次数: 2

Highly automated and efficient simulation environment with UVM 高度自动化和高效的模拟环境与UVM

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834923

Hung-Yi Yang

引用次数: 11

Two-staged parallel layer-aware partitioning for 3D designs 面向3D设计的两阶段并行分层感知划分

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834861

Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang

引用次数: 2

SAT-based complete logic implication with application to logic optimization 基于sat的完整逻辑蕴涵及其在逻辑优化中的应用

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834869

Yung-Chih Chen, Kung-Ming Ji

{"title":"SAT-based complete logic implication with application to logic optimization","authors":"Yung-Chih Chen, Kung-Ming Ji","doi":"10.1109/VLSI-DAT.2014.6834869","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834869","url":null,"abstract":"Logic implication that finds necessary assignments for a given set of value assignments in a Boolean circuit has a wide set of applications in the computer-aided design field, such as logic optimization, design verification, and test pattern generation. Due to the high computational complexity, earlier methods either cannot or do not find all necessary assignments, limiting their qualities in the applications. With the dramatic advance of Boolean satisfiability (SAT) solving techniques, applying the efficient SAT solving techniques to logic implication seems promising. Thus, the paper presents a SAT-based method for complete logic implication. Given a set of value assignments, it first simulates a large number of random patterns and collects a set of candidate necessary assignments based on the simulation results. Then, instead of validating each candidate one by one, it iteratively calls a SAT solver to identify the invalid candidates and remove them. At each SAT solving iteration, at least one invalid candidate can be removed. Finally, only the valid candidates are left and they are exactly all the necessary assignments. Furthermore, we extend the method to compute all mandatory assignments for a stuck-at fault test and apply the extended method to enhance a logic optimization algorithm whose quality largely depends on the completeness of the mandatory assignment computation. The experimental results show that the enhanced method achieves an average of 1.3× improvement in circuit size reduction with acceptable CPU time overhead.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"432 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122872615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0