A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils

Taisuke Hayashi, N. Miura, K. Yoshikawa, M. Nagata
{"title":"A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils","authors":"Taisuke Hayashi, N. Miura, K. Yoshikawa, M. Nagata","doi":"10.1109/VLSI-DAT.2014.6834894","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2014.6834894","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.
一种利用电感增强耦合键合线线圈的无源供电谐振抑制滤波器
提出了一种低功耗、紧凑的无源电源谐振抑制滤波器。利用片上波形监测器,现场分析了功率输送网络(PDN)阻抗,包括封装和板上PDN,以识别SR频率fSR。一个由耦合键合线线圈和片上MOS电容器组组成的陷波滤波器被自动调谐用于SR抑制。与有源SR抑制电路相比,这种无源滤波方法将功率损耗降低到1/5~1/10,静态功率实际上为零[1]。耦合键合线圈增强了其自感,从而缩小了片上电容的尺寸,节省了布局面积。0.18μm CMOS测试芯片显示SR抑制>43%,功耗仅< 7%,布局面积损失< 0.034mm。
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