Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test

Will reliability limit Moore's law?

Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047092 A. Oates

Apply high-level synthesis design and verification methodology on floating-point unit implementation

Pub Date : 2014-06-16 DOI: 10.1109/VLSI-DAT.2014.6834921 Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu

Full system simulation framework for integrated CPU/GPU architecture

Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834872 Po-Han Wang, Gen-Hong Liu, J. Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Siyi Liu, James Greensky