Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test最新文献_第3页

Scaling trends and challenges of advanced memory technology 先进存储技术的扩展趋势和挑战

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839634

Seok-Hee Lee

{"title":"Scaling trends and challenges of advanced memory technology","authors":"Seok-Hee Lee","doi":"10.1109/VLSI-TSA.2014.6839634","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839634","url":null,"abstract":"Summary form only given. DRAM and NAND technologies have been successfully developed so far thanks to advanced patterning and device technologies, meeting high density, high performance and low cost requirements. However, imminent scaling limit in DRAM and NAND requires breakthrough technologies to meet market needs. DRAM technology in 1xnm and beyond faces severe challenges, such as difficulties in obtaining sufficient storage capacitance and sensing margin. To alleviate the problems, new materials for cell capacitor should be exploited and systematic aids such as error correction should be considered. Besides these scaling issues, DRAM has been suffering from performance issue, and it requires enhanced peripheral transistor performance with low power and high speed by using new process technologies such as HKMG. A 3D integration with TSV provides a new solution for high density, high speed, low power, and wider bandwidth without traditional device geometric scaling. However, 3D has its own challenges such as high manufacturing cost and reliability that need to be overcome before it could be widely used. 3D NAND flash memory technologies have been studied as a strong contender due to their potential for replacing conventional 2D floating gate cell. Recently, there has been remarkable progresses towards mass production even though their inherent issues of poor data retention and process complexity. Several challenges such as process, material, and cell architecture will be discussed. New non-volatile memories such as ReRAM, PRAM and STT-MRAM have undergone explosive study in the past decade. ReRAM and PRAM are now leading candidates to replace conventional NAND or NOR flash memories and to pioneer the field of Storage Class Memories, while STT-MRAM is regarded as the only a non-volatile memory that can have the performance of DRAM due to its high-speed read/write and excellent cycling endurance. Device characteristics of new non-volatile memories, key technology of device integration and materials will be discussed.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 360-degree panoramic video system design 360度全景视频系统设计

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834863

Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo

引用次数: 21

All-digital delay-locked loop for 3D-IC die-to-die clock synchronization 用于3D-IC模对模时钟同步的全数字延迟锁定环路

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834902

Ching-Che Chung, Chi-Yu Hou

引用次数: 8

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth 具有可编程带宽的3x过采样混合时钟和数据恢复电路

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834881

Jia-An Jheng, W. Chang, Tai-Cheng Lee

引用次数: 1

A fast transient and under/overshoot suppression DC-DC Buck converter with ACP control 具有ACP控制的快速瞬态和欠/超调抑制DC-DC降压变换器

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834887

Jing Lin, J. Shiau, Chien-Hung Tsai

引用次数: 0

An FPGA implementation of high-throughput key-value store using Bloom filter 基于布隆滤波器的高吞吐量键值存储的FPGA实现

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834868

J. Cho, Kiyoung Choi

引用次数: 15

Keep-Out-Zone analysis for three-dimensional ICs 三维集成电路的保出区分析

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834862

Mostafa Said, M. El-Sayed, Farhad Mehdipour, N. Miyakawa

引用次数: 3

Energy efficiency in the Internet of Things — Critical or nice-to-have? 物联网中的能源效率——至关重要还是值得拥有?

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834913

Yen-kuang Chen

引用次数: 0

On efficient error-tolerability evaluation and maximization for image processing applications 图像处理应用中误差容忍度的有效评估与最大化

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834866

Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng

{"title":"On efficient error-tolerability evaluation and maximization for image processing applications","authors":"Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng","doi":"10.1109/VLSI-DAT.2014.6834866","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834866","url":null,"abstract":"With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131724130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging 基于晶圆级芯片规模封装的新型功率噪声模拟方法

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834875

Yipin Wu, Zhigang Hao, Jin-Seop Han, Joy Tsai

引用次数: 0