A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging

Abstract

Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. The proposed method correctly models the coupling effect from on-die power mesh's current, via mutual inductance, into the WIFI RX path. The proposed method is applied to a wireless combo chip to confirm that simulation correlates well with silicon measurement. As a result, we are able to demonstrate that on-die power mesh optimization can lead to significant reduction in WIFI de-sense.