Keep-Out-Zone analysis for three-dimensional ICs

Mostafa Said, M. El-Sayed, Farhad Mehdipour, N. Miyakawa
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引用次数: 3

Abstract

One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.
三维集成电路的保出区分析
3d集成的主要挑战之一是面积开销,这有两个主要原因:首先是巨大的TSV直径,通常在微米范围内,第二个原因是由于制造过程中产生的高诱导热应力而导致的隔离区(KOZ)开销。除了制造工艺本身外,面积开销对整体良率和制造成本产生反作用,因此面积的增加会降低良率,增加制造成本。本文研究了KOZ开销对总面积、成品率和制造成本的影响。此外,还检查了可能改变KOZ开销的各种参数。我们表明,与tsv相比,KOZ引起的面积开销份额要高得多。此外,为了更准确地估计3d集成电路的W2W总良率和制造成本,还考虑了KOZ的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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