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A discrete-time AAF with clock-efficient chargedomain filter for high attenuation and bandwidth 具有高衰减和带宽的具有时钟效率的电荷域滤波器的离散时间AAF
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357253
Ming-Feng Huang, Szu-Hsien Wu, Tzu-Yi Yang
{"title":"A discrete-time AAF with clock-efficient chargedomain filter for high attenuation and bandwidth","authors":"Ming-Feng Huang, Szu-Hsien Wu, Tzu-Yi Yang","doi":"10.1109/ASSCC.2009.5357253","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357253","url":null,"abstract":"A discrete-time (DT) anti-alias filter (AAF) with clock-efficient charge-domain filter (CECDF) for high attenuation and bandwidth was developed. This AAF possesses 88.86-dB attenuation and 13-MHz bandwidth at a 600-MS/s input-clock rate (ICR) and a 100-MS/s output-sample rate. The measured gain and IIP3 are 12.2-dB and 0-dBm, respectively, consuming only 5.56-mA from a 1.36-V power supply. The chip including clock-logical circuits occupies 0.2-mm2 in 90-nm CMOS logical process.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131060554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer 250Mb/s到3gb /s的5倍过采样接收器，带有全数字自适应均衡器
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357151
Min-Chung Chou, Qui-Ting Chen, Ping-Yu Chen
{"title":"A 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer","authors":"Min-Chung Chou, Qui-Ting Chen, Ping-Yu Chen","doi":"10.1109/ASSCC.2009.5357151","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357151","url":null,"abstract":"In this paper, a 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer is presented. A novel oversampling based inter-symbol interference (ISI) monitor and adapting flows are proposed for the equalizer to compensate channel losses. The receiver has been implemented in 65-nm CMOS process. The analog equalizer has a power consumption of 9.6 mW and an area of 0.012 mm2 including an all-digital ISI monitor and an adapting circuit. The core area of the receiver is 0.26 mm2, including the input terminations, the shared PLL, and three data channels.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130226906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Weak inversion for ultra low-power and very low-voltage circuits 超低功耗和极低压电路的弱反转
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357240
E. Vittoz
{"title":"Weak inversion for ultra low-power and very low-voltage circuits","authors":"E. Vittoz","doi":"10.1109/ASSCC.2009.5357240","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357240","url":null,"abstract":"This paper discusses techniques, limitations and possible future developments of circuits based on transistors operated in the weak inversion (w.i.) mode, also called sub-threshold mode. In analog circuits, w.i. is reached at very low current, but it is also needed for very low supply voltage. Its exponential behaviour can be exploited in special circuits schemes, some of them devised for bipolar transistors. For digital circuits, it can provide the ultimate speed/power ratio in a given process.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128430728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A 658KGates e-streaming video decoder for digital home applications 658KGates电子流视频解码器，用于数字家庭应用
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357236
Chi-Cheng Ju, Kung-Sheng Lin, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, F. Chiu, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, Ginny Chen, T. Hsiao, Joe Chen
{"title":"A 658KGates e-streaming video decoder for digital home applications","authors":"Chi-Cheng Ju, Kung-Sheng Lin, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, F. Chiu, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, Ginny Chen, T. Hsiao, Joe Chen","doi":"10.1109/ASSCC.2009.5357236","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357236","url":null,"abstract":"The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658K logic gates and 522Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder [1]. It explores RV temporal reference method, RV VLD table reduction, multi-stage pipeline and memory management unit to facilitate cost and bandwidth efficiency for digital home and internet services. The test chip is fabricated and the first using 55nm CMOS process which occupies 658KGates/522Kbits SRAM on die and dissipates 195mW in full HD@30fps RV playback.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121783342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control 一种具有预测延迟调整方案的低功耗宽范围时钟同步器，用于DVFS控制中的连续电压缩放
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357185
M. Onouchi, Y. Kanno, Makoto Saen, S. Komatsu, Y. Yasu, K. Ishibashi
{"title":"A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control","authors":"M. Onouchi, Y. Kanno, Makoto Saen, S. Komatsu, Y. Yasu, K. Ishibashi","doi":"10.1109/ASSCC.2009.5357185","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357185","url":null,"abstract":"A “wide-range voltage-and-frequency clock synchronizer” (WRCS) for maintaining synchronization during voltage-scaling transition during dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the WRCS is so-called predictive-delay-adjustment (PDA) scheme based on a relative skew measure. The PDA scheme reduces the area of the WRCS by 77%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65×10−3 mm2. It was demonstrated for the first time that measured jitter is suppressed to less than 6.8% of clock period in the case of wide-range voltage variation (0.8–1.55 V) and wide frequency range (100 MHz–1 GHz). Moreover, current dissipation of the WRCS is only 0.48 mA at 1.1-V 100-MHz operation.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121723771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS imager and 2-D light pulse receiver array for spatial optical communication 用于空间光通信的CMOS成像仪和二维光脉冲接收器阵列
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357192
M. Sarkera, Isamu Takai, M. Andoh, K. Yasutomi, S. Itoh, S. Kawahito
{"title":"A CMOS imager and 2-D light pulse receiver array for spatial optical communication","authors":"M. Sarkera, Isamu Takai, M. Andoh, K. Yasutomi, S. Itoh, S. Kawahito","doi":"10.1109/ASSCC.2009.5357192","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357192","url":null,"abstract":"This paper presents a CMOS imager and 2-D Light Pulse Receiver (LPR) array for car-to-car and road-to-car spatial optical communication. Using the prototype sensor with 640×240 image pixels and 640×240 LPR cells implemented with 0.18μm CMOS technology. Both imaging and 60fps optical communication at the carrier frequency of 1MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrent shows that the spatial optical communication up to 100m is possible.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122027405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 128Mb ChainFeRAMTM and system designs for HDD application and enhanced HDD performance 128Mb ChainFeRAMTM和系统设计，用于硬盘应用和增强的硬盘性能
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357235
D. Takashima, Yasushi Nagadomi, K. Hatsuda, Y. Watanabe, S. Fujii
{"title":"A 128Mb ChainFeRAMTM and system designs for HDD application and enhanced HDD performance","authors":"D. Takashima, Yasushi Nagadomi, K. Hatsuda, Y. Watanabe, S. Fujii","doi":"10.1109/ASSCC.2009.5357235","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357235","url":null,"abstract":"This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, the 128Mb ChainFeRAMTM design and power supply system design to meet HDD application are presented. Second, the concept of nonvolatile FeRAM cache and the simulated and measured HDD performance improvement are presented. The read/write bandwidth improvements to 1.12 times, 3.3 times and 1.9 times have been obtained by bench mark tests of PC Mark 05 and FD Bench v1.01, and by PC user data for 5 days, respectively. These results have been the same level of or more effective than the results of HDD rotational speed-up from 5400rpm to 7200rpm using DRAM cache. The write energy is reduced by 25% in PC Mark05 test.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129598467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity 5Gb/s低功耗PCI express/USB3.0就绪PHY，采用40nm CMOS技术，具有高抗抖动能力
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357154
M. Lin, Chien-Chun Tsai, Chih-Hsien Chang, Y. Peng, Tsung-Hsin Yu, Jinn-Yeh Chien, Wei-Chih Chen, Chi-Chang Lu, Wei-Chih Chen, Jimmy Fu, Shu-Chun Yang, Chien-Hung Chen, K. Deng, Chin-Hua Wen, Li-Wen Wang
{"title":"A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity","authors":"M. Lin, Chien-Chun Tsai, Chih-Hsien Chang, Y. Peng, Tsung-Hsin Yu, Jinn-Yeh Chien, Wei-Chih Chen, Chi-Chang Lu, Wei-Chih Chen, Jimmy Fu, Shu-Chun Yang, Chien-Hung Chen, K. Deng, Chin-Hua Wen, Li-Wen Wang","doi":"10.1109/ASSCC.2009.5357154","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357154","url":null,"abstract":"A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40nm CMOS technology. With the implementation of one lane transceiver, PLL, and PCS, the experimental results have shown this test chip passes PCI Express 2.0/1.0 TX compliance test and RX compliance test. It also achieves receiver jitter tolerance up to 0.33UI at BER of 10-12 with stressing all spec. specified jitter sources. A compact area of 510um×710um for one lane has been achieved while consuming only 125mW from 0.9V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129753903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Circuits for silicon photonics on a “macrochip” “宏芯片”上的硅光子学电路
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357232
R. Ho, J. Lexau, Frankie Y. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, Xuezhe Zheng, J. Cunningham, A. Krishnamoorthy
{"title":"Circuits for silicon photonics on a “macrochip”","authors":"R. Ho, J. Lexau, Frankie Y. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, Xuezhe Zheng, J. Cunningham, A. Krishnamoorthy","doi":"10.1109/ASSCC.2009.5357232","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357232","url":null,"abstract":"Recent advances in silicon photonics bring significant benefits to “macrochip” grids made of arrayed chips. Such configurations have global interconnects long enough to benefit from the high speed, low energy, and high bandwidth density of optics. In this paper we consider the constraints of large macrochip systems, and explore modulator drivers and photodetector receivers that match those constraints. We show measured results from a recent 90 nm testchip intended to mate with optical components.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129816022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 6.4GT/s point-to-point unidirectional link with full current compensation 具有全电流补偿的6.4GT/s点对点单向链路
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357156
H. Muljono, K. Tian, M. Atha, Charlie Lin, Linda K Sun, S. Rusu
{"title":"A 6.4GT/s point-to-point unidirectional link with full current compensation","authors":"H. Muljono, K. Tian, M. Atha, Charlie Lin, Linda K Sun, S. Rusu","doi":"10.1109/ASSCC.2009.5357156","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357156","url":null,"abstract":"This 45nm 1.1V unidirectional differential point-to-point link interface achieves 6.4GT/s transfer rate. To support 17 inches, 2-connector channel topology required by MultiProcessor (MP) platform, it utilizes two novel current compensation techniques that optimize the performance/power ratio of the transmitter output swing level and receiver gain/bandwidth.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"34 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120857901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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