{"title":"250Mb/s到3gb /s的5倍过采样接收器，带有全数字自适应均衡器","authors":"Min-Chung Chou, Qui-Ting Chen, Ping-Yu Chen","doi":"10.1109/ASSCC.2009.5357151","DOIUrl":null,"url":null,"abstract":"In this paper, a 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer is presented. A novel oversampling based inter-symbol interference (ISI) monitor and adapting flows are proposed for the equalizer to compensate channel losses. The receiver has been implemented in 65-nm CMOS process. The analog equalizer has a power consumption of 9.6 mW and an area of 0.012 mm2 including an all-digital ISI monitor and an adapting circuit. The core area of the receiver is 0.26 mm2, including the input terminations, the shared PLL, and three data channels.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer\",\"authors\":\"Min-Chung Chou, Qui-Ting Chen, Ping-Yu Chen\",\"doi\":\"10.1109/ASSCC.2009.5357151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer is presented. A novel oversampling based inter-symbol interference (ISI) monitor and adapting flows are proposed for the equalizer to compensate channel losses. The receiver has been implemented in 65-nm CMOS process. The analog equalizer has a power consumption of 9.6 mW and an area of 0.012 mm2 including an all-digital ISI monitor and an adapting circuit. The core area of the receiver is 0.26 mm2, including the input terminations, the shared PLL, and three data channels.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer
In this paper, a 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer is presented. A novel oversampling based inter-symbol interference (ISI) monitor and adapting flows are proposed for the equalizer to compensate channel losses. The receiver has been implemented in 65-nm CMOS process. The analog equalizer has a power consumption of 9.6 mW and an area of 0.012 mm2 including an all-digital ISI monitor and an adapting circuit. The core area of the receiver is 0.26 mm2, including the input terminations, the shared PLL, and three data channels.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
