A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control

Abstract

A “wide-range voltage-and-frequency clock synchronizer” (WRCS) for maintaining synchronization during voltage-scaling transition during dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the WRCS is so-called predictive-delay-adjustment (PDA) scheme based on a relative skew measure. The PDA scheme reduces the area of the WRCS by 77%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65×10−3 mm2. It was demonstrated for the first time that measured jitter is suppressed to less than 6.8% of clock period in the case of wide-range voltage variation (0.8–1.55 V) and wide frequency range (100 MHz–1 GHz). Moreover, current dissipation of the WRCS is only 0.48 mA at 1.1-V 100-MHz operation.