Chi-Cheng Ju, Kung-Sheng Lin, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, F. Chiu, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, Ginny Chen, T. Hsiao, Joe Chen
{"title":"A 658KGates e-streaming video decoder for digital home applications","authors":"Chi-Cheng Ju, Kung-Sheng Lin, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, F. Chiu, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, Ginny Chen, T. Hsiao, Joe Chen","doi":"10.1109/ASSCC.2009.5357236","DOIUrl":null,"url":null,"abstract":"The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658K logic gates and 522Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder [1]. It explores RV temporal reference method, RV VLD table reduction, multi-stage pipeline and memory management unit to facilitate cost and bandwidth efficiency for digital home and internet services. The test chip is fabricated and the first using 55nm CMOS process which occupies 658KGates/522Kbits SRAM on die and dissipates 195mW in full HD@30fps RV playback.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658K logic gates and 522Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder [1]. It explores RV temporal reference method, RV VLD table reduction, multi-stage pipeline and memory management unit to facilitate cost and bandwidth efficiency for digital home and internet services. The test chip is fabricated and the first using 55nm CMOS process which occupies 658KGates/522Kbits SRAM on die and dissipates 195mW in full HD@30fps RV playback.
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