M. Lin, Chien-Chun Tsai, Chih-Hsien Chang, Y. Peng, Tsung-Hsin Yu, Jinn-Yeh Chien, Wei-Chih Chen, Chi-Chang Lu, Wei-Chih Chen, Jimmy Fu, Shu-Chun Yang, Chien-Hung Chen, K. Deng, Chin-Hua Wen, Li-Wen Wang
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A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity
A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40nm CMOS technology. With the implementation of one lane transceiver, PLL, and PCS, the experimental results have shown this test chip passes PCI Express 2.0/1.0 TX compliance test and RX compliance test. It also achieves receiver jitter tolerance up to 0.33UI at BER of 10-12 with stressing all spec. specified jitter sources. A compact area of 510um×710um for one lane has been achieved while consuming only 125mW from 0.9V supply.
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