A 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer

Abstract

In this paper, a 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer is presented. A novel oversampling based inter-symbol interference (ISI) monitor and adapting flows are proposed for the equalizer to compensate channel losses. The receiver has been implemented in 65-nm CMOS process. The analog equalizer has a power consumption of 9.6 mW and an area of 0.012 mm2 including an all-digital ISI monitor and an adapting circuit. The core area of the receiver is 0.26 mm2, including the input terminations, the shared PLL, and three data channels.