发布求助
文献互助 智能选刊 最新文献

2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献

筛选
英文 中文
Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors 基于符号聚焦压缩器的高效高速近似符号乘法器
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548436
Yi Guo, Heming Sun, S. Kimura
{"title":"Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors","authors":"Yi Guo, Heming Sun, S. Kimura","doi":"10.1109/SOCC46988.2019.1570548436","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548436","url":null,"abstract":"Approximate computing has emerged as a promising approach to reduce energy by sacrificing some accuracy in error-tolerant applications. For these applications, multiplication is a key fundamental operation. In the paper, we propose an approximate signed multiplier design with a low power consumption and a short critical path. Inexact sign-focused compressors are first proposed to accumulate partial products, which cut the carry propagation and simplify the circuit complexity. Moreover, three types of approximate multipliers are presented to achieve different trade-offs between accuracy loss and hardware saving. Experimental results show that the most accurate proposed multiplier reduces power by 52.44%, area by 37.73%, and delay by 22.14%, compare with the exact signed multiplier. In addition, the proposed multiplier design costs less hardware than other multipliers with a comparable accuracy. At last, an application to image processing shows the efficiency of proposed signed multipliers.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117002177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A BJT-Based Temperature Sensor in 40-nm CMOS With ±0.8°C(3σ) Untrimmed Inaccuracy 基于bjt的40纳米CMOS温度传感器，误差为±0.8°C(3σ)
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555725
Tantan Zhang, Yuan Gao
{"title":"A BJT-Based Temperature Sensor in 40-nm CMOS With ±0.8°C(3σ) Untrimmed Inaccuracy","authors":"Tantan Zhang, Yuan Gao","doi":"10.1109/SOCC46988.2019.1570555725","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555725","url":null,"abstract":"This paper presents a bipolar junction transistor (BJT) based temperature sensor in 40-nm CMOS process with improved untrimmed accuracy. By exploiting the relation between saturation current and recombination current at the base of BJT, the combined base current is optimized to compensate the process spread of base-emitter voltage (VBE). In addition, a robust MOS resistor is proposed to further reduce the variations in the collector current as well as the VBE. Compared to the conventional weighted combination of resistors with complementary temperature coefficient, the proposed MOS resistor can reduce the variations by 3.2$times$. An energy-efficient incremental ADC (IADC) digitizes the temperature dependent $V_{B E}$ and $Delta V_{B E}$. The prototype achieves an untrimmed inaccuracy of $pm 0.8^{circ} mathrm{C}(3 sigma)$ at $1 mathrm{kSa} / mathrm{s}$ over -20$^{circ}mathbf{C}simmathbf{100}^{circ}mathbf{C}$. The sensor draws $11.2 mumathbf{A}$ at room temperature under $1.2-mathrm{V}$ supply, making it a promising candidate for application in systems-on-chip (SoC) thermal monitoring.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s 从硬件角度看ChaCha密码:从476片到175 Gbit/s比特率的可扩展chachha8/12/20实现
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548289
J. Pfau, Maximilian Reuter, T. Harbaum, K. Hofmann, J. Becker
{"title":"A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s","authors":"J. Pfau, Maximilian Reuter, T. Harbaum, K. Hofmann, J. Becker","doi":"10.1109/SOCC46988.2019.1570548289","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548289","url":null,"abstract":"AES (Advanced Encryption Standard) accelerators are commonly used in high-throughput applications, but they have notable resource requirements. We investigate replacing the AES cipher with ChaCha ciphers and propose the first ChaCha FPGA implementations optimized for data throughput. In consequence, we compare implementations of three different system architectures and analyze which aspects dominate the performance of those.Our experimental results indicate that a bandwidth of 175 Gbit/s can be reached with as little as 2982 slices, whereas comparable state of the art AES accelerators require 10 times as many slices [1]. Taking advantage of the flexibility inherent in the ChaCha cipher, we also demonstrate how our implementation scales to even higher throughputs or lower resource usage (down to 476 slices), benefiting applications which previously could not employ cryptography because of resource limitations.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124722988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique 利用相位差积累技术进行边缘计算的0.8% BER 1.2 pJ/bit基于仲裁器的PUF
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570537105
A. Do
{"title":"0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique","authors":"A. Do","doi":"10.1109/SOCC46988.2019.1570537105","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570537105","url":null,"abstract":"CMOS PUF is getting more attention from both research community and the industry because it allows cost-efficient integration of device’s digital signature for highly secured authentication protocols. Leveraged on usually-undesirable uncontrollable and random variations in CMOS fabrication process, many CMOS PUF implementations provide strong entropy source to construct low-power, unique and unpredictable device-specific fingerprints. One of the most critical issues in deploying PUFs is their stability against noise and environment conditions when they are interrogated with the same challenge at different time and conditions. This is usually characterized by the native bit-error rate (BER) or intra-class Hamming distance. We propose an arbiter-based PUF utilizing Ring-Oscillators in conjunction with a phase accumulation technique to minimize the BER. Its implementation in 65 nm CMOS consumes only 1. 2pJ/bit while having an error rate of 0.8%.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121218596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
WF: Ph.D. Forum 博士论坛
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088100
{"title":"WF: Ph.D. Forum","authors":"","doi":"10.1109/socc46988.2019.9088100","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088100","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126653661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT using Stationary Neuromorphic Vision Sensors EBBIOT:一种基于静止神经形态视觉传感器的物联网监控低复杂度跟踪算法
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570553690
Jyotibdha Acharya, Andrés Ussa Caycedo, Vandana Padala, Rishi Raj Sidhu Singh, G. Orchard, Bharath Ramesh, A. Basu
{"title":"EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT using Stationary Neuromorphic Vision Sensors","authors":"Jyotibdha Acharya, Andrés Ussa Caycedo, Vandana Padala, Rishi Raj Sidhu Singh, G. Orchard, Bharath Ramesh, A. Basu","doi":"10.1109/SOCC46988.2019.1570553690","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570553690","url":null,"abstract":"In this paper, we present EBBIOT-a novel paradigm for object tracking using stationary neuromorphic vision sensors in low-power sensor nodes for the Internet of Video Things (IoVT). Different from fully event based tracking or fully frame based approaches, we propose a mixed approach where we create event-based binary images (EBBI) that can use memory efficient noise filtering algorithms. We exploit the motion triggering aspect of neuromorphic sensors to generate region proposals based on event density counts with >1000X less memory and computes compared to frame based approaches. We also propose a simple overlap based tracker (OT) with prediction based handling of occlusion. Our overall approach requires 7X less memory and 3X less computations than conventional noise filtering and event based mean shift (EBMS) tracking. Finally, we show that our approach results in significantly higher precision and recall compared to EBMS approach as well as Kalman Filter tracker when evaluated over 1.1 hours of traffic recordings at two different locations.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127342385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
W2A: Securing Your Chip W2A:保护你的芯片
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088019
{"title":"W2A: Securing Your Chip","authors":"","doi":"10.1109/socc46988.2019.9088019","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088019","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131947982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection 带有频率误差检测的10ghz快锁全数字频率合成器
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555475
G. Luo, Ching-Yuan Yang
{"title":"A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection","authors":"G. Luo, Ching-Yuan Yang","doi":"10.1109/SOCC46988.2019.1570555475","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555475","url":null,"abstract":"This paper presents a 10-GHz all-digital phaselocked loop (ADPLL) frequency synthesizer with a fast-locked technique. The proposed fast-locked technique uses two mechanisms that optimize each other. One enhances the capability of frequency-tracking, the other uses a method for detecting frequency-error to improve the efficiency of frequencytracking. The ADPLL synthesizer is fabricated in a 0.18 um CMOS process, and its operating frequency is from 9.4 GHz to 10.4 GHz. The total power consumption is 30.6mW with 1.8V supply voltage. The locked time is 0.88 us and 190 us with and without the fast-locked technique when the frequency hopping distance is 400 MHz, respectively.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"15 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132846297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
W1C: Special Session I: Energy Efficient Custom Computing with FPGAs W1C:专题会议I:基于fpga的节能定制计算
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9087989
{"title":"W1C: Special Session I: Energy Efficient Custom Computing with FPGAs","authors":"","doi":"10.1109/socc46988.2019.9087989","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9087989","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121407491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications 一种全数字温度传感器，具有过程和电压变化公差，适用于物联网应用
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570557014
Ching-Che Chung, Hsin-Han Huang
{"title":"An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications","authors":"Ching-Che Chung, Hsin-Han Huang","doi":"10.1109/SOCC46988.2019.1570557014","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570557014","url":null,"abstract":"The embedded temperature sensor which monitors the hot spots of the chip had become an essential circuit for improving the reliability of the system-on-a-chip (SoC). However, most of the temperature sensors cannot resist the influence of voltage variations and results in significant temperature errors. In this paper, the relative reference modeling (RRM)-based temperature sensor is presented. The proposed temperature sensor uses a low-temperature sensitivity voltage classifier and a low-voltage sensitivity proportional to absolute temperature (PTAT) circuit to resist the voltage variations. Addition, the process variations can be eliminated after the three-point calibration. The proposed temperature sensor was fabricated in TSMC 90nm CMOS process. The measured results show that the temperature error of the proposed design is from -1.47°C to 1.40°C with supply voltage 0.9 to 1.1V.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信