2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献

Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms 基于量子算法的高空间分辨率数据高效模式识别降维

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558150

Naveed Mahmud, E. El-Araby

{"title":"Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms","authors":"Naveed Mahmud, E. El-Araby","doi":"10.1109/SOCC46988.2019.1570558150","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558150","url":null,"abstract":"With the promising advancement in quantum computing technology in the last decade, there is a strong motivation to find suitable applications for quantum algorithms and quantum computers. Domains such as High Energy Physics (HEP) have an enormous readout count of high-resolution data. Performing pattern recognition on this readout is computationally challenging and time-consuming because of the multi-dimensionality of the data. In this paper, we propose a methodology that employs quantum algorithms such as Quantum Wavelet Transform and Grover’s search algorithm for timeefficient pattern recognition in data sets that are characterized by high spatial resolution and high dimensionality. The motivation behind using quantum algorithms is the potential speedup relative to classical methods, when performed by a quantum computer. In our proposed methodology, Quantum Wavelet Transform is performed on the high spatial resolution data to reduce its dimensionality while quantum Grover’s search algorithm is employed to search for target patterns in the reduced data set. Performing the search operation on data with reduced spatial resolution, minimizes processing overheads and computation times. Moreover, use of quantum techniques yield faster results, compared to classical dimension reduction and search methods. We demonstrate the feasibility of the proposed methodology by emulating the quantum algorithms on classical hardware based on field programmable gate arrays (FPGAs). A high performance reconfigurable computer (HPRC) was used for the experimental evaluation. The obtained results are favorable towards our proposed approach.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs 用于fpga容错应用的能量-面积高效近似乘法器

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548202

N. Toan, Jeong-Gun Lee

引用次数: 5

N2 OC: Neural-Network-on-Chip Architecture N2 OC:片上神经网络架构

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548351

Kasem Khalil, Omar Eldash, Ashok Kumar, M. Bayoumi

{"title":"N2 OC: Neural-Network-on-Chip Architecture","authors":"Kasem Khalil, Omar Eldash, Ashok Kumar, M. Bayoumi","doi":"10.1109/SOCC46988.2019.1570548351","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548351","url":null,"abstract":"Neural networks are increasingly being used in many applications because of their ability to solve complex problems. In order to increase the processing speed of neural networks, hardware-based techniques are being actively researched in the literature. However, implementing a neural network using conventional hardware design methods is a complex and challenging task for hardware designers as there are many hyperparameters and trade-offs that need to be examined in depth. This paper presents a novel Neural-Network-on-Chip (N2OC) to provide a hardware implementation of a neural network based on network-on-chip. The proposed approach provides reconfigurability when the number of nodes per layer varies depending on the desired performance and application. The proposed method provides a flexible hardware implementation of a neural network where the number and order of nodes can be controlled. Two datasets have been used for testing the proposed method, and the proposed method has a comparable result with the state-of-the-art. The hardware design is implemented using VHDL and Altera Arria 10 GX FPGA 10AX115N2F45E1SG. Throughput and average delay of the network are studied, and the simulation result shows the design has stable performance. On a problem studied (in handwritten digits classification), the proposed method has an accuracy of 99.24% while the state-of-the-art has an accuracy of 98.17%.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130563351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

W1A: RF, Analog & Mixed Signal Circuits I W1A:射频，模拟和混合信号电路1

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088109

引用次数: 0

A Digital-Enhanced Interferometric Radar Sensor for Physiological Sign Monitoring 一种用于生理信号监测的数字增强干涉雷达传感器

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570571644

Zhongyuan Fang, Liheng Lou, Kai Tang, Ting Guo, Bo Chen, Yisheng Wang, Chuanshi Yang, Longjie Zhong, Yuanjin Zheng

引用次数: 0

Co-Design of Highly Uniform ReRAM Arrays in 180nm CMOS Technology for Neuromorphic Systems 基于180nm CMOS技术的神经形态系统高均匀ReRAM阵列协同设计

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570553076

V. Y. Zhuo, Weijie Wang, Zhixian Chen, Hock-Koon Lee, Minghua Li, W. Song

引用次数: 1

W3B: Wireline & Wireless Communication W3B:有线和无线通信

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088038

引用次数: 0

SOCC 2019 Front Matters SOCC 2019前沿事项

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088062

引用次数: 0

An Efficient Implementation of Arbiter PUF on FPGA for IoT Application 物联网应用中仲裁PUF在FPGA上的高效实现

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548268

Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, B. Sen

{"title":"An Efficient Implementation of Arbiter PUF on FPGA for IoT Application","authors":"Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, B. Sen","doi":"10.1109/SOCC46988.2019.1570548268","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548268","url":null,"abstract":"Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the Internet of Things (IoT). However, like other technologies, FPGA needs resilience against various threats. In addition, the un-monitored environment makes IoT devices more vulnerable. In this context, Physically Unclonable Function (PUF) can provide a low-cost and unique security solution over the costly conventional cryptographic system. Although Arbiter PUF (APUF) is the most suitable PUF variant for IoT, implementing a high-quality APUF on FPGA has been proved to be challenging. To date, programmable delay logic (PDL) is the widely adopted primitive to design APUF on FPGA. However, the implementation of PDL based APUF demands hard-macro feature of CAD tool which limits flexibility of the design. Also, such designs require fine-tuning to achieve PUF characteristics. This paper introduces a new switching structure named path changing switch (PCS) which is easily implementable on FPGA, and this PCS is used here to design APUF instead of the PDL. Further, the directed routing constraint is used to implement an exemplary APUF which possess better flexibility. Also, a new structure of the enable logic and manual routing is used to reduce the delay-bias. Finally, the design has been implemented over 15 different Spartan 3E FPGA boards. Experimental results show that the proposed design outperforms the PDL based APUFs in terms of PUF quality metrics without using additional fine-tuning. Also, the implemented design shows significant tolerance against temperature variations.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124547744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

ITUS: A Secure RISC-V System-on-Chip 一个安全的RISC-V片上系统

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570564307

Vinay B. Y. Kumar, A. Chattopadhyay, Jawad Haj-Yahya, A. Mendelson

引用次数: 11