2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献_第2页

A Neural-Network-Based Non-linear Interference Cancellation Scheme for Wireless IoT Backhaul with Dual-Connectivity 一种基于神经网络的双连接无线物联网回程非线性干扰消除方案

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570559857

Huiliang Zhang, Zhonglong Wang, Fei Qin, Meng Ma, Jianhua Zhang

{"title":"A Neural-Network-Based Non-linear Interference Cancellation Scheme for Wireless IoT Backhaul with Dual-Connectivity","authors":"Huiliang Zhang, Zhonglong Wang, Fei Qin, Meng Ma, Jianhua Zhang","doi":"10.1109/SOCC46988.2019.1570559857","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570559857","url":null,"abstract":"In this paper, we consider an Internet of Things (IoT) wireless network using Long Term Evolution (LTE) cellular system as backhaul. To provide high throughput, by using dual-connectivity technique, the IoT gateway simultaneously connects to two evolved Node Bs (eNBs) on two carriers, one for downlink and the other for uplink. As a result, the receive link will be severely interfered by the harmonic interference (HI) and inter-modulation (IM) components caused by the imperfections of power amplifier (PA) and in-phase/quadrature (I/Q) modulator. To solve this problem, in this paper, an neural-network (NN)based non-linear interference cancellation scheme is proposed for dual-connectivity IoT gateway. In the proposed scheme, the nonlinear interference is first reconstructed by using the transmit signal and the trained NN in baseband, and then subtracted from the received signal in digital domain at receiver. The NN precisely models the link behavior from the baseband transmitter to the baseband receiver, including all the linear and non-linear effect. Additionally, the NN can be used to reconstruct and cancel not only the HI, but also the IM components of the mirror-frequency interference (MFI) caused by I/Q imbalance, and direct current (DC) bias caused by local oscillator (LO) leakage. To evaluate the performance of the proposed scheme, a hardware prototype is designed and implemented. Experimental results show that the proposed scheme has a superior performance in dual-connectivity system compared with the traditional non-linear interference cancellation scheme using polynomial (PM) model.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124064142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

SOCC 2019 Additional Reviewers SOCC 2019额外审稿人

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088008

引用次数: 0

W2B: Digital Signal Processing W2B:数字信号处理

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088108

引用次数: 0

Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis FPGA高级综合中MGS-QRD算法的环路优化

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548480

Chong Yeam Tan, C. Y. Ooi, N. Ismail

引用次数: 2

AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design AxC-CS:硬件高效压缩感知编码器设计的近似计算

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558477

Wenfeng Zhao, Biao Sun, Jian Chen, Yajun Ha

{"title":"AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design","authors":"Wenfeng Zhao, Biao Sun, Jian Chen, Yajun Ha","doi":"10.1109/SOCC46988.2019.1570558477","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558477","url":null,"abstract":"In this paper, we present an approximate computing framework for hardware-efficeint compressed sensing encoder design exploiting application-level error-resiliency, termed as AxC-CS (underline {A}pprounderline {x}imate underline {C}omputing for underline {C}ompressed underline {S}ensing). We consider a 2-stage scalar quantization scheme during CS encoding process for physiological signals in sensor nodes and demonstrate numerically that bringing forward the quantization process to the input signals could lead to negligible difference in signal reconstruction as compared to the standard measurement quantization scheme, and a second stage quantization over the approximate measurement can be performed to restore the ratedistortion performance. The optimal quantization depth can be deterministic according to the adopted sensing matrices. For random binary sensing matrix adopted in this paper, [${mathbf{log}}_{mathbf{2}} (mathbf{n}/2)/2$] bits quantization depth can be safely truncated without incuring noticable errors when $ell_{1} -$minimization is used for signal recovery. Compared with standard CS with accurate operation, this leads to efficient CS encoder design with simultaneous area and power reduction, where 25% and 28% lower area and power consumption can be achieved on MIT-BIH Arrhythmia database, respectively.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130072591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Group Delay Compensation By Combining 3-tap FFE With CTLE for 80Gbps-PAM4 Optical Transmitter 80Gbps-PAM4光发射机三分接FFE与CTLE相结合的群延迟补偿

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570537232

Jiquan Li, Yingmei Chen, Zhen Zhang, Hui Wang, Chao Guo, Binbin Yang

引用次数: 0

Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs 时间感知封装单元减少预键合测试在3d - ic

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570544200

Pei-An Ho, Yen-Hao Chen, A. Wu, TingTing Hwang

{"title":"Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs","authors":"Pei-An Ho, Yen-Hao Chen, A. Wu, TingTing Hwang","doi":"10.1109/SOCC46988.2019.1570544200","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570544200","url":null,"abstract":"Three dimensional integrated circuits (3D-ICs) have being developed to improve existing 2D designs by providing smaller chip areas, higher performance and lower power consumption. With the short and dense through-silicon-vias (TSVs), multiple dies can be integrated to overcome the barrier of interconnection. However, before 3D-ICs become a viable technology, the understanding of 3D testing issues is still insufficient and there are still many unresolved testing challenges. To ensure the stack yield of future adopting of 3D-ICs, pre-bond testing is needed to provide the known good die (KGD). Since the TSVs are not fully accessible prior to bonding, testing the combinational logic between the scan flip-flops and TSV becomes a complex issue. In order to overcome the limitation of TSV, additional wrapper cells were inserted at the two ends of TSVs to provide controllability and observability [1], [2]. Even though it is a major breakthrough solution for pre-bond testing, the wrapper cells used by the TSVs lead to significant area overhead. Further, to reduce area overhead, the existing primary scan flip-flops were reused to achieve high testability [3], [4]. However, practical timing considerations were overlooked and the number of inserted wrapper cells was still high. In this paper, we present an enhanced method to not only generate more reused scan flip-flops but also not incur any timing violation by using an accurate timing model. Furthermore, testability constraints are also considered and can be traded-off between area overhead and testability. The experimental results on ITC99 benchmark circuits [5] have shown that our method can reduce 0.92%-6.01% wrapper cells with competitive testability compared to the previous work.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126860391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and Modeling of Passive LC Filters Using Node Elimination Technique 基于节点消去技术的无源LC滤波器分析与建模

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570547047

S. Hamedi-Hagh

引用次数: 0

Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function 高精度和硬件高效卷积函数的折叠和确定性随机MAC

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570543844

M. Wong, A. Do

引用次数: 0

A Low Power Analog Front-end for Ultrasound Receiver 一种用于超声接收机的低功耗模拟前端

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570572046

Chuanshi Yang, Kai Tang, Lei Qiu, Zhongyuan Fang, Yuanjin Zheng

引用次数: 0