Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs

Abstract

Three dimensional integrated circuits (3D-ICs) have being developed to improve existing 2D designs by providing smaller chip areas, higher performance and lower power consumption. With the short and dense through-silicon-vias (TSVs), multiple dies can be integrated to overcome the barrier of interconnection. However, before 3D-ICs become a viable technology, the understanding of 3D testing issues is still insufficient and there are still many unresolved testing challenges. To ensure the stack yield of future adopting of 3D-ICs, pre-bond testing is needed to provide the known good die (KGD). Since the TSVs are not fully accessible prior to bonding, testing the combinational logic between the scan flip-flops and TSV becomes a complex issue. In order to overcome the limitation of TSV, additional wrapper cells were inserted at the two ends of TSVs to provide controllability and observability [1], [2]. Even though it is a major breakthrough solution for pre-bond testing, the wrapper cells used by the TSVs lead to significant area overhead. Further, to reduce area overhead, the existing primary scan flip-flops were reused to achieve high testability [3], [4]. However, practical timing considerations were overlooked and the number of inserted wrapper cells was still high. In this paper, we present an enhanced method to not only generate more reused scan flip-flops but also not incur any timing violation by using an accurate timing model. Furthermore, testability constraints are also considered and can be traded-off between area overhead and testability. The experimental results on ITC99 benchmark circuits [5] have shown that our method can reduce 0.92%-6.01% wrapper cells with competitive testability compared to the previous work.