Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function

Abstract

A family of Stochastic Computing (SC) circuit using folded and deterministic sequence is presented in this work. The SC circuit produces shorter and higher progressive precision sequences, and without the use of PRNG (often implemented as LFSR in hardware). Using the new stochastic representation, a design of SC multiply-and-accumulate (MAC) function is proposed and implemented as hardware convolution accelerator on a Virtex-4 FPGA. Experimental results obtained from detailed test analysis has proven that the new SC-MAC unit has higher computational accuracy and achieved a better ratio of throughput performance over area cost (hardware efficiency) in comparison with the conventional SC approach.