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2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献

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Efficient Hardware Acceleration of Convolutional Neural Networks 卷积神经网络的高效硬件加速
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570573948
S. Kala, B. R. Jose, J. Mathew, N. Sivanandan
{"title":"Efficient Hardware Acceleration of Convolutional Neural Networks","authors":"S. Kala, B. R. Jose, J. Mathew, N. Sivanandan","doi":"10.1109/SOCC46988.2019.1570573948","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570573948","url":null,"abstract":"Convolutional neural networks (CNNs) have emerged as the most efficient technique for solving a host of machine learning tasks. Compute and memory intensive nature of CNN has stimulated lot of work in hardware acceleration of these network models. FPGAs have emerged as a promising approach for accelerating CNNs, due to its high performance, flexibility and energy efficiency. We propose a unified architecture named UniWiG, where both Winograd based convolution and general matrix multiplication (GEMM) can be accelerated using the same set of processing elements. Proposed architecture has been used to accelerate AlexNet and VGG-16 models on FPGA with a performance of 433.63 GOPS and 407.23 GOPS respectively. We have also analyzed the performance with varying Winograd tile sizes and found out the most appropriate tile sizes for maximizing the performance while reducing on-chip memory resource.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134517696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications 用于宽带射频片上系统的数字可控无源变斜率增益均衡器
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558481
S. Lakshminarayanan, K. Hofmann
{"title":"A Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications","authors":"S. Lakshminarayanan, K. Hofmann","doi":"10.1109/SOCC46988.2019.1570558481","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558481","url":null,"abstract":"A wideband fully integrated digitally controlled high linearity RF gain slope equalizer is presented in this work. The gain slope equalizer is realized using a modified bridged T attenuation network. The bridged resistor in the network is digitally controlled using a combination of series resistors connected in parallel to NMOS switches to vary the attenuation level. A gain slope tuning range of 2.39 dB/GHz to 6 dB/GHz is achieved for a frequency band of 200 MHz to 1.85 GHz. The effectiveness of the proposed equalizer circuit is demonstrated by integration on an RF transceiver ASIC. The digital controllability makes the proposed circuit highly suitable for system-on-chip RFICs.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116868143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS 一种45 Gb/s、98 fJ/bit、0.02 mm2、峰值专用电感的65纳米CMOS跨阻放大器
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548520
A. Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, H. Fukuyama, Naoki Miura, H. Nosaka, H. Onodera
{"title":"A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS","authors":"A. Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, H. Fukuyama, Naoki Miura, H. Nosaka, H. Onodera","doi":"10.1109/SOCC46988.2019.1570548520","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548520","url":null,"abstract":"This paper demonstrates a small area, high speed and low power CMOS transimpedance amplifier (TIA) for optical communication. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Based on the bandwidth and energy per bit estimation, we designed a 5-stage INV-TIA and on-chip inductors for inductive peaking. The TIA is fabricated in a 65-nm CMOS and it operates at 45 Gb/s with 49 dBO transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency. Small footprint design of inductors realizes the area of 0.02 mm2 though three inductors are used.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115891354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 100 KS/s 8–10 bit resolution-reconfigurable SAR ADC for bioelectronics application 用于生物电子学应用的100 KS/s 8-10位分辨率可重构SAR ADC
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555766
Yunfeng Hu, Lisheng Chen, Hui Chen, Yi Wen, Huabin Zhang, Xiaojia Liu
{"title":"A 100 KS/s 8–10 bit resolution-reconfigurable SAR ADC for bioelectronics application","authors":"Yunfeng Hu, Lisheng Chen, Hui Chen, Yi Wen, Huabin Zhang, Xiaojia Liu","doi":"10.1109/SOCC46988.2019.1570555766","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555766","url":null,"abstract":"A 8–10 bit resolution-reconfigurable SAR ADC for bioelectronics application is proposed. The ADC consists of resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, and the resolution-control SAR logic. Simulated in 180 nm CMOS process, the ADC achieves the 49.77/55.65/61.36 dB signal-to-noise and distortion ratio (SNDR) and 67.56/71.94/78.41 dB spurious-free dynamic range (SFDR) at 100 kS/s sampling rate with the power consumption of $0.81/0.91/ 1.01 mu mathrm{W}$.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124866937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
F1B: Special Session VI: SoC Architecture and Circuit for IoT Applications-II F1B:专题会议六:面向物联网应用的SoC架构与电路- ii
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088041
{"title":"F1B: Special Session VI: SoC Architecture and Circuit for IoT Applications-II","authors":"","doi":"10.1109/socc46988.2019.9088041","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088041","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125414169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
F2A: RF, Analog and Mixed-signal Circuits II F2A:射频，模拟和混合信号电路2
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088064
{"title":"F2A: RF, Analog and Mixed-signal Circuits II","authors":"","doi":"10.1109/socc46988.2019.9088064","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088064","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129937430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises 一种用于下肢运动实时监测的智能单传感器装置
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548017
Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
{"title":"A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises","authors":"Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang","doi":"10.1109/SOCC46988.2019.1570548017","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548017","url":null,"abstract":"Studies have shown that stair exercises can enhance the strength of lower limbs for patients with limb disorders. However, there are only few systems that can monitor the lower limb exercises in the medical institutes. To analyze the lower limb exercises instantaneously, we propose a smart single-sensor wearable device, $S^{3}-Sock$, equipped on shoes. The sock can monitor and measure the stride count, step height, and the distance of step trajectory about lower limb exercises. The experimental results demonstrate that the proposed system is reliable under different lower limb exercises. The averages of absolute mean errors of stride count in stair-climbing and walking are about 2.00% and 0.88%, respectively. The averages of absolute mean errors of step height are about 5.12% and 8.23% in step-by-step and step-over-step stair climbing, respectively.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
eNVM based In-memory Computing for Intelligent and Secure Computing Systems 基于eNVM的智能安全计算系统内存计算
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570557582
Kejie Huang, Chuyun Qin
{"title":"eNVM based In-memory Computing for Intelligent and Secure Computing Systems","authors":"Kejie Huang, Chuyun Qin","doi":"10.1109/SOCC46988.2019.1570557582","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570557582","url":null,"abstract":"The recent breakthrough in Artificial Intelligence (AI) largely relies on the advance of hardware performance. However, energy and security have been primary concerns in the design and management of modern computing systems and data centers. The emerging embedded Non-Volatile Memories (eNVMs) have drawn great attention to various applications to improve both computing speed and security with much lower power consumption. In this paper, we review and discuss several application cases of the in-memory computing techniques, including Deep Neural Network (DNN) accelerators and neuromorphic computing circuits. Moreover, we also explore the in-memory computing techniques for the security enhancement, especially for machine learning attack. The emerging security issues raised by eNVMs and possible solutions are also discussed.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125643213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
F2B: Special Session VII: Integrated Wearable Electromagnetic-Acoustics Sensing Circuits and Systems Towards SoC Chip Integratione F2B:专题会议七:面向SoC芯片集成的集成可穿戴电磁声学传感电路和系统
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088020
{"title":"F2B: Special Session VII: Integrated Wearable Electromagnetic-Acoustics Sensing Circuits and Systems Towards SoC Chip Integratione","authors":"","doi":"10.1109/socc46988.2019.9088020","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088020","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121962833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scalable DU Architecture for IoT massive connection 面向物联网海量连接的可扩展DU架构
2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558152
Kuhwa sung, Terng-Yin Hsu
{"title":"Scalable DU Architecture for IoT massive connection","authors":"Kuhwa sung, Terng-Yin Hsu","doi":"10.1109/SOCC46988.2019.1570558152","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558152","url":null,"abstract":"this paper explains a new efficiency architecture of scalable-DU as Wireless Processing Unit. It is proposed that how to accelerate the computing capability of eNB. The legacy multiprocessor architecture always is master-slave which need a control center to balance the usage of resource and making job assignments efficiently. Scalable-DU as Wireless Processing Units no need to have one control center to do these things and can execute jobs by themselves. It can be more adjustable and efficient for the assignment of the jobs and resource management. Besides, this thesis also designs the architecture of ALU which to support the various arithmetic calculations for the purpose of communication.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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