2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献_第4页

W3C: Special Session III: FPGA-based Processor for Intelligent Sensing W3C:专题会议III:基于fpga的智能传感处理器

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088080

引用次数: 0

Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming 基于几何规划的最小能量实时任务动态供电电压电平生成

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555698

H. Manohara, B. Harish

{"title":"Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming","authors":"H. Manohara, B. Harish","doi":"10.1109/SOCC46988.2019.1570555698","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555698","url":null,"abstract":"Communication and computation are moving towards mobile platforms to address the demands of emerging applications. Despite advances in process and battery technologies that allow processors to provide much greater computation per unit of energy and longer life of battery, the fundamental tradeoff between performance and battery life continues to remain critical. To maximize energy efficiency of processors in mobile electronics, Dynamic Voltage Scaling (DVS) is conventionally deployed to dynamically vary supply voltage and hence speed, at run time. The nonlinear relationship between CPU speed and power consumption enables spread out of task execution in time domain by leveraging on the available slackness by reducing voltage, than to run the CPU at full speed for short bursts and then switch to idle state. The proposed work aims to minimize the energy consumption of each task of real time periodic task sets, in a uniprocessor environment, using task utilization factor as a control variable for generating the optimized supply voltage to every task of task sets. The energy minimization of a task is implemented using Geometric Programming (GP), by varying frequency over a range on fixed task sets and on randomly varying task set instances and hence generating supply voltage levels. Results demonstrate that energy savings vary between 18% to 34%, for standard task sets and an average of 77% for randomly generated task sets, depending on the power delay characteristics of task sets.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fused Multiply-Add for Variable Precision Floating-Point 可变精度浮点数的融合乘加运算

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555329

A. Nannarelli

引用次数: 2

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem RISC-V生态系统中十进制计算软硬件协同设计的周期精度评估

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570559752

Riaz-ul-haque Mian, Michihiro Shintani, M. Inoue

引用次数: 1

ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation 基于二元高斯混合模型估计的ml热传感器标定

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570561880

W. Kuo, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang

引用次数: 0

A Glitch Key-Gate for Logic Locking 用于逻辑锁定的故障钥匙门

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570547988

De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang

引用次数: 1

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks 一种高效的事件驱动深度脉冲神经网络神经形态架构

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548305

Duy-Anh Nguyen, Duy-Hieu Bui, F. Iacopi, Xuan-Tu Tran

{"title":"An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks","authors":"Duy-Anh Nguyen, Duy-Hieu Bui, F. Iacopi, Xuan-Tu Tran","doi":"10.1109/SOCC46988.2019.1570548305","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548305","url":null,"abstract":"Deep Neural Networks (DNNs) have been successfully applied to various real-world machine learning applications. However, performing large DNN inference tasks in real-time remains a challenge due to its substantial computational costs. Recently, Spiking Neural Networks (SNNs) have emerged as an alternative way of processing DNN’fs task. Due to its eventbased, data-driven computation, SNN reduces both inference latency and complexity. With efficient conversion methods from traditional DNN, SNN exhibits similar accuracy, while leveraging many state-of-the-art network models and training methods. In this work, an efficient neuromorphic hardware architecture for image recognition task is presented. To preserve accuracy, the analog-to-spiking conversion algorithm is adopted. The system aims to minimize hardware area cost and power consumption, enabling neuromorphic hardware processing in edge devices. Simulation results have shown that, with the MNIST digit recognition task, the system has achieved $times 20$ reduction in terms of core area cost compared to the state-of-the-art works, with an accuracy of 94.4%, core area of 15 $mu m^{2}$ at a maximum frequency of 250 MHz.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128589156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Accelerating Binary-Matrix Multiplication on FPGA 在FPGA上加速二进制矩阵乘法

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570544215

Debjyoti Bhattacharjee, A. Chattopadhyay, Ricardo Jack Liwongan

引用次数: 0

SOCC 2019 Technical Program Committee SOCC 2019技术计划委员会

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088086

引用次数: 0

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications 流数据应用中固定深度管道寄存器需求最小化

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548393

T. Goldbrunner, N. Doan, Diogo Poças, Thomas Wild, A. Herkersdorf

引用次数: 0