{"title":"Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs","authors":"Seungseok Nam, E. Matús, G. Fettweis","doi":"10.1109/SOCC46988.2019.1570555815","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555815","url":null,"abstract":"One of the key challenges for design of highly-scalable wireless signal processing SoCs is to guarantee application determinism and responsiveness in order to meet the strict timing requirements. Time-division-multiplex network-on-chip (NoC) in conjunction with dynamic connection allocation is a promising approach for guaranteed service in NoC allowing efficient use of resources by adapting path-allocation to traffic statistics. Most recently, the trellis path-search algorithm (TESSA) demonstrated excellent performance as well as HW implementation efficiency by exploiting low-complexity shortest available path-search algorithm. However, the lack of path-cost knowledge in the path selection procedure need not necessarily lead to the most efficient resource usage that might result in the reduction of allocation rate and hence also system performance. This work tackles this problem by introducing path-cost factor into path-search algorithm than enables to select optimum path in terms of both the path-length and path-cost respectively. In this regards, we propose soft branch metric to characterize both the path-availability as well as path-costs that results in the shortest-available and lowest-cost path (SALC) selection algorithm. In addition to this and in contrast to recent work, we propose an application specific instruction processor enabling efficient and flexible implementation of proposed path search algorithm. Execution cycles of the implemented processor in 8x8 2D mesh is about seven thousand times faster than 32bits RISC processor. The simulations using 6x6 2D-mesh TDM-NoC with 12 time-slots showed up to 31% and 7% success rate improvement for uniformly distributed Poisson traffic and Splash2-benchmark, respectively.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"48 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"T1C: Special Session IV: eNVM based In-Memory Computing for Intelligent and Secure SoCs","authors":"","doi":"10.1109/socc46988.2019.9088097","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088097","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131190116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SOCC 2019 Welcome Message from the Technical Program Chairs","authors":"","doi":"10.1109/socc46988.2019.9088082","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088082","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114080649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MSMPX: Microarchitectural Extensions for Meltdown Safe Memory Protection","authors":"G. Krishnakumar, C. Rebeiro","doi":"10.1109/SOCC46988.2019.1570564578","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570564578","url":null,"abstract":"In recent years several hardware enforced pointer protection schemes have been proposed. The most notable amongst them is the Intel MPX, which can identify spatial violations at run time. Recently, it is shown that Intel MPX is vulnerable to a potent attack called Meltdown, which exploits the processor’s transient behavior during speculative execution.In this paper, we show that there is a fundamental design flaw in Intel MPX and all other hardware enforced pointer protection schemes that we surveyed, making all of them vulnerable to Meltdown. We then suggest a design strategy called MSMPX, that provides hardware enforced pointer protection, while at the same time being immune to Meltdown. We compare the hardware overheads on an OpenRISC processor and the performance overheads with respect to Intel MPX.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SOCC 2019 Message from the Conference General Chairs","authors":"","doi":"10.1109/socc46988.2019.9088029","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088029","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC","authors":"Weixiong Jiang, Heng Yu, Y. Ha","doi":"10.1109/SOCC46988.2019.1570558174","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558174","url":null,"abstract":"Dynamic Voltage and Frequency Scaling (DVFS) has been extensively applied as a system-level methodology for energy optimization or temperature control. But current DVFS systems are mostly implemented on CPUs, DVFS working on FPGAs is limited. Moreover, all current DVFS systems available for FPGAs have either low scaling resolution or long reconfiguration time, and none of them is easy to reuse. In this paper, we develop a fast and efficient ZYNQ-based DVFS platform with high resolution and short reconfiguration time. In addition, we add the DVFS support to SDSoC and make it easier and quicker to build an ZYNQ system with DVFS features. We also apply our DVFS platform to a real-time semi-global matching (SGM) accelerator as a case study, and develop a DVFS policy to optimize its power consumption. Compared to the state-of-the-art, our DVFS platform saves 45% FFs and almost all LUTs, the voltage scaling time is 7ms and the frequency scaling time is 3$mu s$, and time for one design iteration to add DVFS support is reduced from several hours to a few minutes. Compared to its unoptimized version, the SGM accelerator with our DVFS platform saves up to 46% energy.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}