{"title":"tdm - noc中动态连接分配的专用指令处理器","authors":"Seungseok Nam, E. Matús, G. Fettweis","doi":"10.1109/SOCC46988.2019.1570555815","DOIUrl":null,"url":null,"abstract":"One of the key challenges for design of highly-scalable wireless signal processing SoCs is to guarantee application determinism and responsiveness in order to meet the strict timing requirements. Time-division-multiplex network-on-chip (NoC) in conjunction with dynamic connection allocation is a promising approach for guaranteed service in NoC allowing efficient use of resources by adapting path-allocation to traffic statistics. Most recently, the trellis path-search algorithm (TESSA) demonstrated excellent performance as well as HW implementation efficiency by exploiting low-complexity shortest available path-search algorithm. However, the lack of path-cost knowledge in the path selection procedure need not necessarily lead to the most efficient resource usage that might result in the reduction of allocation rate and hence also system performance. This work tackles this problem by introducing path-cost factor into path-search algorithm than enables to select optimum path in terms of both the path-length and path-cost respectively. In this regards, we propose soft branch metric to characterize both the path-availability as well as path-costs that results in the shortest-available and lowest-cost path (SALC) selection algorithm. In addition to this and in contrast to recent work, we propose an application specific instruction processor enabling efficient and flexible implementation of proposed path search algorithm. Execution cycles of the implemented processor in 8x8 2D mesh is about seven thousand times faster than 32bits RISC processor. The simulations using 6x6 2D-mesh TDM-NoC with 12 time-slots showed up to 31% and 7% success rate improvement for uniformly distributed Poisson traffic and Splash2-benchmark, respectively.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"48 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs\",\"authors\":\"Seungseok Nam, E. Matús, G. Fettweis\",\"doi\":\"10.1109/SOCC46988.2019.1570555815\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"One of the key challenges for design of highly-scalable wireless signal processing SoCs is to guarantee application determinism and responsiveness in order to meet the strict timing requirements. Time-division-multiplex network-on-chip (NoC) in conjunction with dynamic connection allocation is a promising approach for guaranteed service in NoC allowing efficient use of resources by adapting path-allocation to traffic statistics. Most recently, the trellis path-search algorithm (TESSA) demonstrated excellent performance as well as HW implementation efficiency by exploiting low-complexity shortest available path-search algorithm. However, the lack of path-cost knowledge in the path selection procedure need not necessarily lead to the most efficient resource usage that might result in the reduction of allocation rate and hence also system performance. This work tackles this problem by introducing path-cost factor into path-search algorithm than enables to select optimum path in terms of both the path-length and path-cost respectively. In this regards, we propose soft branch metric to characterize both the path-availability as well as path-costs that results in the shortest-available and lowest-cost path (SALC) selection algorithm. In addition to this and in contrast to recent work, we propose an application specific instruction processor enabling efficient and flexible implementation of proposed path search algorithm. Execution cycles of the implemented processor in 8x8 2D mesh is about seven thousand times faster than 32bits RISC processor. The simulations using 6x6 2D-mesh TDM-NoC with 12 time-slots showed up to 31% and 7% success rate improvement for uniformly distributed Poisson traffic and Splash2-benchmark, respectively.\",\"PeriodicalId\":253998,\"journal\":{\"name\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"48 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC46988.2019.1570555815\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC46988.2019.1570555815","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs
One of the key challenges for design of highly-scalable wireless signal processing SoCs is to guarantee application determinism and responsiveness in order to meet the strict timing requirements. Time-division-multiplex network-on-chip (NoC) in conjunction with dynamic connection allocation is a promising approach for guaranteed service in NoC allowing efficient use of resources by adapting path-allocation to traffic statistics. Most recently, the trellis path-search algorithm (TESSA) demonstrated excellent performance as well as HW implementation efficiency by exploiting low-complexity shortest available path-search algorithm. However, the lack of path-cost knowledge in the path selection procedure need not necessarily lead to the most efficient resource usage that might result in the reduction of allocation rate and hence also system performance. This work tackles this problem by introducing path-cost factor into path-search algorithm than enables to select optimum path in terms of both the path-length and path-cost respectively. In this regards, we propose soft branch metric to characterize both the path-availability as well as path-costs that results in the shortest-available and lowest-cost path (SALC) selection algorithm. In addition to this and in contrast to recent work, we propose an application specific instruction processor enabling efficient and flexible implementation of proposed path search algorithm. Execution cycles of the implemented processor in 8x8 2D mesh is about seven thousand times faster than 32bits RISC processor. The simulations using 6x6 2D-mesh TDM-NoC with 12 time-slots showed up to 31% and 7% success rate improvement for uniformly distributed Poisson traffic and Splash2-benchmark, respectively.