2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献

{"title":"T2C: Special Session V: Hardware Security","authors":"","doi":"10.1109/socc46988.2019.9088087","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9088087","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Protecting the Integrity of Processor Cores with Logic Encryption","authors":"Dominik Sisejkovic, Farhad Merchant, R. Leupers","doi":"10.1109/SOCC46988.2019.1570564157","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570564157","url":null,"abstract":"Malicious circuit modifications known as hardware Trojans represent a rising threat to the integrated circuit supply chain. Logic encryption has emerged as a prominent technique for protecting the integrity of circuit designs. In recent years, an extensive amount of logic encryption algorithms have been introduced. However, existing approaches focus on isolated circuit components without considering the modularity and complexity of modern hardware designs. In this work, we focus on several aspects of protecting modern processor core designs. Firstly, we discuss Inter-Lock, a novel approach to scaling logic encryption to multi-module hardware designs by leveraging inter-module dependencies. Inter-Lock is efficiently able to exponentially increase the security and render attacks on isolated modules infeasible by undermining the basic assumption that the key inputs are known [3]. Secondly, we present Control-Lock, a methodology for protecting critical inter-module control signals in hardware designs against software-controlled hardware Trojans [2]. Both techniques are evaluated on a RISC-V processor core with respect to the area, delay and power overhead. Lastly, we briefly discuss a unifying logic encryption metric as well as acceptable overheads for widely used benchmarks [4] [1].","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126482890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A NAND Flash Endurance Prediction Scheme with FPGA-based Memory Controller System","authors":"Zhuo Chen, Yuqian Pan, Mingyang Gong, Haichun Zhang, Mingyu Zhang, Zhenglin Liu","doi":"10.1109/SOCC46988.2019.1570552892","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570552892","url":null,"abstract":"The endurance of NAND flash memory continues to decrease with process scaling, leading to a decline in the reliability of the storage system and a rise on risk of data corruption. To enhance the reliability of the storage system, we utilize a neural network model with high accuracy and full application, to predict how far each block of a NAND flash can be cycled before the uncorrectable data errors occur. The input to the model includes program-time, erase-time and raw bit error (RBE) measured by FPGA (Field-Programmable Gate Array) and its output is a specific numerical value of endurance. Based on this prediction model, we propose a FPGA-based scheme for real-time endurance prediction with an accuracy of over 90%.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131599761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Error-latency Trade-off for Asynchronous Stochastic Computing with ΣΔ Streams for the IoT","authors":"Patricia Gonzalez-Guerrero, S. G. Wilson, M. Stan","doi":"10.1109/SOCC46988.2019.1570548453","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548453","url":null,"abstract":"Asynchronous stochastic computing (ASC) using continuous-time-asynchronous $SigmaDelta$ modulators $(mathrm{S}mathrm{C}-mathrm{A}SigmaDelta mathrm{M})$ has the potential to enable ultra-low-power, on-node machine learning algorithms for the next generation of sensors for the Internet of Things $(mathrm{I}mathrm{o}mathrm{T})$. Similar to synchronous stochastic computing $(mathrm{S}mathrm{S}mathrm{C}^{mathrm{I}})$1, in $mathrm{S}mathrm{C}-mathrm{A}SigmaDelta mathrm{M}$ complex processing units can be implemented with simple gates because numbers are represented with streams. For example a multiplier is implemented with a XNOR gate, yielding savings in power and area of 90% compared with the typical binary approach. Previous work demonstrated that $mathrm{S}mathrm{C}-mathrm{A}SigmaDelta mathrm{M}$ leverages SSC advantages and addresses its drawbacks, achieving significant savings in energy, power and latency. In this work, we study a theoretical model to determine the fundamental limits of accuracy and computing time for SC- $mathrm{A}SigmaDelta mathrm{M}$. Since the $SigmaDelta$ streams are periodic the final computing error is non-zero and depends on the period of the input streams. We validate our theoretical model with Spice-level simulations and evaluate the power and energy consumption using a standard FinFetlX2 technology for two cases: 1) multiplication and 2) gamma correction, an image processing algorithm. Our work determines circuit design guidelines for $mathrm{S}mathrm{C}-mathrm{A}SigmaDelta mathrm{M}$ and shows that multiplication with $mathrm{S}mathrm{C}-mathrm{A}SigmaDelta mathrm{M}$ requires at least 6X less time than SSC. The latency reduction and novel architecture positively impacts the overall energy consumption in the $mathrm{I}mathrm{o}mathrm{T}$ node, enabling savings in energy of 79% compared with the binary approach.1SC is by definition a synchronous approach, thus we use SSC to differentiate it from asynchronous stochastic computing2In modern technologies the node number does not refer to any one feature in the process, and foundries use slightly different conventions; we use lx to denote the 14/16nm FinFET nodes offered by the foundry.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130879405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images","authors":"S. Kadiyala, V. Pudi, Mohit Garg, H. Ngo, S. Lam, T. Srikanthan","doi":"10.1109/SOCC46988.2019.1570555870","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555870","url":null,"abstract":"Principal Component Analysis (PCA) has been a major tool in performing characterization of environmental data where in, the data is typically a hyper spectral image. Using statistical methods, PCA is often capable of reducing the dimensionality of data. On the other hand Nonlinear Iterative PArtial Least Squares (NIPALS) algorithm provides an efficient alternative for extracting the principal components with a minimum penalty on processing speed. In this work we provide the hardware implementation of NIPALS algorithm on an FPGA, for extracting principal components of a given dataset. Experimental results of our approach on various hyper spectral images show 92.31% average reduction in dimensionality with 0.1% average loss on information of the dataset. The results obtained from XILINX Artix-7 FPGA implementation show the advantage of the proposed method. More particularly, the proposed architecture gives an improvement in speed by factor of 15.71x compared to the state of art approaches.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130887377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip","authors":"Luka Daoud, N. Rafla","doi":"10.1109/SOCC46988.2019.1570548660","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548660","url":null,"abstract":"Due to the impact of ongoing deep sub-micron technology, billions of transistors are crammed in an integrated circuit to combine multiple systems on a single chip. Network-on-Chip (NoC) has become the communication infrastructure among these systems’ components. On the other hand, scaling down the feature size has increased the probability of faults which could be experienced in runtime. Therefore, online fault detection is considered in the system design. This paper presents an efficient method to detect and avoid faulty nodes that silently discard packets from the network. This method deals with control faults of the NoC routers, where the packets are received but are not saved in the buffers. In this work, a high level fault model is proposed. Also, a detection technique and fault tolerant method is presented. The proposed scheme is analyzed and evaluated. The results show 3.91%, 9.97%, and 8.82% overhead in area, power, and performance, respectively, while guaranteeing packet delivery to the destination.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124285776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-based object detection processor with HOG feature and SVM classifier","authors":"F. An, Peng Xu, Zhihua Xiao, Chao Wang","doi":"10.1109/SOCC46988.2019.1570558044","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558044","url":null,"abstract":"Computer vision is an important sensing technique to translate the information to decisions. In robotic applications, object detection is a critical skill to perform tasks for robots in complex environments. The deep-learning framework, e.g. You Only Look Once (YOLO), attracts much more attention recently. Moreover, it is not an optimal solution for a mobile robot since it requires a large scale of hardware resources, on-chip SRAMs, and power consumption. In this work, we report an object detection processor synchronizing the image sensor in FPGA with a cellbased histogram of oriented gradient (HOG) feature descriptor and support vector machine (SVM) classifier by parallel sliding window mechanism. The HOG feature extraction circuitry with pixel-based pipelined architecture constructs the cell-based feature vectors for parallelizing partial SVM-based classification in multiple sliding windows. The SVM classification produces the final result after accumulating the vector components in one sliding window. This framework can be used to both localize and recognize multiple objects in video footage. The proposed object processor, in which the SVM classifier is trained by INRIA datasets, is implemented and verified on Intel Stratix IV FPGA for the pedestrian.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114815895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications","authors":"Samuel Rigault, N. Moeneclaey, L. Labrak, I. O’Connor","doi":"10.1109/SOCC46988.2019.1570548090","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548090","url":null,"abstract":"A fully integrated laser diode driver being currently manufactured in 40nm CMOS technology is presented. It is dedicated for fast sub-ns laser pulses generation with the aim of improving accuracy and resolution of SPAD-based time-of-flight (TOF) rangefinder in mobile devices. The proposed driver circuit is based on capacitive charge transfer. Its specific features are a voltage doubler design for increase laser power at low input voltage (<3V), as well as a reverse bias voltage scheme to address typical laser diode slow turn-off transient (optical tail). Simulation results based on electro-optical laser diode model and post-layout extraction shows that, for a 2.5V supply voltage, the driver can produce a typical 460ps laser drive current pulse up to 230mA. With these settings, a 208ps laser pulse with a 238mW peak power is generated. In addition, the current pulse width can be configured down to 375ps to generate sub-100ps laser pulses. The power consumption of the proposed driver circuit is 113mW at 200MHz repetition rate.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115902634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"T1B: Design Optimization for Approximate Computing","authors":"","doi":"10.1109/socc46988.2019.9087988","DOIUrl":"https://doi.org/10.1109/socc46988.2019.9087988","url":null,"abstract":"","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"115 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116641228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18 μm SiGe BiCMOS Technology","authors":"Hui Wang, Yingmei Chen, Yuan Gao, Ning Li, Zhen Zhang, Chao Guo, Jiquan Li","doi":"10.1109/SOCC46988.2019.1570541947","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570541947","url":null,"abstract":"low noise and high linearity 56Gbaud PAM4 transimpedance amplifier (TIA) is presented in this paper, and it meets the requirements of emerging 400G Ethernet standards. The inductive shunt feedback technique is used in input stage of TIA to meet the specifications of high bandwidth and low noise. A Continuous-time linear equalizer (CTLE) is cascaded after TIA to compensate loss of bandwidth which caused by Photo Diode (PD) parasitic capacitance. A variable gain amplifier (VGA) which provides 18-dB gain control range accommodates input currents up to 1 mApp with little group delay variation. The TIA is implemented in 0.18μm SiGe BiCMOS technology. Post simulation results show that TIA provides 74.4dB transimpedance gain while bandwidth is 30GHz and input referred noise current is 2.3uArms. The output buffer provides 600mV output swing, and power consumption of the whole four channels is 600mW.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"391 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116664031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}