Hui Wang, Yingmei Chen, Yuan Gao, Ning Li, Zhen Zhang, Chao Guo, Jiquan Li
{"title":"基于0.18 μm SiGe BiCMOS技术的四线性56Gbaud PAM4跨阻放大器","authors":"Hui Wang, Yingmei Chen, Yuan Gao, Ning Li, Zhen Zhang, Chao Guo, Jiquan Li","doi":"10.1109/SOCC46988.2019.1570541947","DOIUrl":null,"url":null,"abstract":"low noise and high linearity 56Gbaud PAM4 transimpedance amplifier (TIA) is presented in this paper, and it meets the requirements of emerging 400G Ethernet standards. The inductive shunt feedback technique is used in input stage of TIA to meet the specifications of high bandwidth and low noise. A Continuous-time linear equalizer (CTLE) is cascaded after TIA to compensate loss of bandwidth which caused by Photo Diode (PD) parasitic capacitance. A variable gain amplifier (VGA) which provides 18-dB gain control range accommodates input currents up to 1 mApp with little group delay variation. The TIA is implemented in 0.18μm SiGe BiCMOS technology. Post simulation results show that TIA provides 74.4dB transimpedance gain while bandwidth is 30GHz and input referred noise current is 2.3uArms. The output buffer provides 600mV output swing, and power consumption of the whole four channels is 600mW.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"391 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18 μm SiGe BiCMOS Technology\",\"authors\":\"Hui Wang, Yingmei Chen, Yuan Gao, Ning Li, Zhen Zhang, Chao Guo, Jiquan Li\",\"doi\":\"10.1109/SOCC46988.2019.1570541947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"low noise and high linearity 56Gbaud PAM4 transimpedance amplifier (TIA) is presented in this paper, and it meets the requirements of emerging 400G Ethernet standards. The inductive shunt feedback technique is used in input stage of TIA to meet the specifications of high bandwidth and low noise. A Continuous-time linear equalizer (CTLE) is cascaded after TIA to compensate loss of bandwidth which caused by Photo Diode (PD) parasitic capacitance. A variable gain amplifier (VGA) which provides 18-dB gain control range accommodates input currents up to 1 mApp with little group delay variation. The TIA is implemented in 0.18μm SiGe BiCMOS technology. Post simulation results show that TIA provides 74.4dB transimpedance gain while bandwidth is 30GHz and input referred noise current is 2.3uArms. The output buffer provides 600mV output swing, and power consumption of the whole four channels is 600mW.\",\"PeriodicalId\":253998,\"journal\":{\"name\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"391 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC46988.2019.1570541947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC46988.2019.1570541947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18 μm SiGe BiCMOS Technology
low noise and high linearity 56Gbaud PAM4 transimpedance amplifier (TIA) is presented in this paper, and it meets the requirements of emerging 400G Ethernet standards. The inductive shunt feedback technique is used in input stage of TIA to meet the specifications of high bandwidth and low noise. A Continuous-time linear equalizer (CTLE) is cascaded after TIA to compensate loss of bandwidth which caused by Photo Diode (PD) parasitic capacitance. A variable gain amplifier (VGA) which provides 18-dB gain control range accommodates input currents up to 1 mApp with little group delay variation. The TIA is implemented in 0.18μm SiGe BiCMOS technology. Post simulation results show that TIA provides 74.4dB transimpedance gain while bandwidth is 30GHz and input referred noise current is 2.3uArms. The output buffer provides 600mV output swing, and power consumption of the whole four channels is 600mW.
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