Accelerating Binary-Matrix Multiplication on FPGA

Abstract

Matrix multiplication is required for a wide variety of applications, including data mining, linear algebra, graph transformations, etc. Most of the existing works to accelerate matrix multiplication have focused on matrices with floating point elements. In this work, we propose for the first time an FPGA based accelerator architecture for binary matrix multiplication. It consists of processing elements laid out in regular tiled manner. The communication structure used is a torus. We undertook detailed experimental study of the proposed architecture. The architecture shows excellent scalability with increase in number of processing elements, with minimal drop in operating frequency. The proposed system achieves maximum throughput of 1120 Gops for $4 \times 4$ network size with $2048 \times 2048$ matrix size. The performance achieved by the system is considerably higher than existing works of floating point multiplication on FPGAs, due to optimized PE design for binary matrix multiplication.