Efficient Hardware Acceleration of Convolutional Neural Networks

Abstract

Convolutional neural networks (CNNs) have emerged as the most efficient technique for solving a host of machine learning tasks. Compute and memory intensive nature of CNN has stimulated lot of work in hardware acceleration of these network models. FPGAs have emerged as a promising approach for accelerating CNNs, due to its high performance, flexibility and energy efficiency. We propose a unified architecture named UniWiG, where both Winograd based convolution and general matrix multiplication (GEMM) can be accelerated using the same set of processing elements. Proposed architecture has been used to accelerate AlexNet and VGG-16 models on FPGA with a performance of 433.63 GOPS and 407.23 GOPS respectively. We have also analyzed the performance with varying Winograd tile sizes and found out the most appropriate tile sizes for maximizing the performance while reducing on-chip memory resource.