A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS

Abstract

This paper demonstrates a small area, high speed and low power CMOS transimpedance amplifier (TIA) for optical communication. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Based on the bandwidth and energy per bit estimation, we designed a 5-stage INV-TIA and on-chip inductors for inductive peaking. The TIA is fabricated in a 65-nm CMOS and it operates at 45 Gb/s with 49 dBO transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency. Small footprint design of inductors realizes the area of 0.02 mm2 though three inductors are used.