ITUS: A Secure RISC-V System-on-Chip

Abstract

The rising tide of attacks, in the recent years, against microprocessors and the system-on-chip (SoC) space as a whole, has led to a growing number of studies into security of SoCs. Security fortification is often incorporated as a follow-up feature to existing systems and many vulnerabilities cannot be patched without significantly degrading performance. A holistic approach to address the security challenge needs to include security-first design principles, security-aware test and verification methodologies, and well-quantified performance trade-off analysis. In this paper, we report the design principles of ITUS 1, a secure SoC based on RISC-V architecture. In parallel, a systematic overview of various design and automation efforts towards achieving SoC security is presented.1after Itus, a relevant name from Greek mythology