2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献_第8页

LIGHTER-R: Optimized Reversible Circuit Implementation For SBoxes LIGHTER-R: sbox可逆电路的优化实现

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548320

Vishnu Asutosh Dasu, Anubhab Baksi, Sumanta Sarkar, A. Chattopadhyay

引用次数: 21

A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL 基于D/PLL的2.7 gb /s时钟数据恢复电路

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548362

You-Sheng Lin, Miao-Shan Li, Ching-Yuan Yang

引用次数: 1

Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications 硬件安全应用中使用NoC平台作为噪声发生器的可重构路由路径

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570557958

Weng-Geng Ho, Ali Akbar Pammu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee

{"title":"Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications","authors":"Weng-Geng Ho, Ali Akbar Pammu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee","doi":"10.1109/SOCC46988.2019.1570557958","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570557958","url":null,"abstract":"We propose a multicore power balancing technique by configuring data routing paths in the 9-core Network-on-Chip (NoC) based platform for hardware security applications, particularly for differential power analysis (DPA) countermeasures. There are three degrees of configurability to hide the leaked data. First, the cores are flexibly-programmable to perform AES operation and dummy operations to moderate the power dissipation. Second, the NoC routers are also flexibly-programmable, further enhancing the power moderation. Third, the cores and their associated routers feature individual controllable clock frequencies to moderate the time that leaks data. These three configurable features collectively balance the power dissipation and enable the time moderation to resist DPA. The 9-core platform IC occupies $sim$1.9 mm2, operates up to 100MHz @1.2V and dissipates 2.46mW @100MHz power. When running Advanced Encryption Standard (AES) operation, the normalized energy deviation (NED) is undesirable high at 0.21 for power-on (1 core + 1 router). By applying the multicore power balancing technique, the NED reduces by $sim$52% when increasing the number of operating routers from 1 to 5, i.e. (1 core + 5 routers), and reduces by $sim$73% when increasing the number of operating cores from 1 to 4, i.e. (4 cores + 4 routers).","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130820357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array 光电场可编程门阵列的辐射退化分析及电路性能改进方法

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548505

Hirotoshi Ito, Minoru Watanabe

引用次数: 0

W2C: Special Session II: SoC Architecture and Circuit for IoT Applications-I W2C:专题会议II:物联网应用的SoC架构和电路- i

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088068

引用次数: 0

A Network on Chip Adapter for Real-Time and Safety-Critical Applications 用于实时和安全关键应用的片上网络适配器

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558594

F. Kempf, Nidhi Anantharajaiah, Leonard Masing, J. Becker

引用次数: 0

Training Deep Neural Networks Using Posit Number System 用正数系统训练深度神经网络

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558530

Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, L. Du

{"title":"Training Deep Neural Networks Using Posit Number System","authors":"Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, L. Du","doi":"10.1109/SOCC46988.2019.1570558530","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558530","url":null,"abstract":"With the increasing size of Deep Neural Network (DNN) models, the high memory space requirements and computational complexity have become an obstacle for efficient DNN implementations. To ease this problem, using reduced-precision representations for DNN training and inference has attracted many interests from researchers. This paper first proposes a methodology for training DNNs with the posit arithmetic, a type-3 universal number (Unum) format that is similar to the floating point(FP) but has reduced precision. A warm-up training strategy and layer-wise scaling factors are adopted to stabilize training and fit the dynamic range of DNN parameters. With the proposed training methodology, we demonstrate the first successful training of DNN models on ImageNet image classification task in 16 bits posit with no accuracy loss. Then, an efficient hardware architecture for the posit multiply-and-accumulate operation is also proposed, which can achieve significant improvement in energy efficiency than traditional floating-point implementations. The proposed design is helpful for future low-power DNN training accelerators.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127786688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A Lossless Astronomical Data Compression Scheme with FPGA Acceleration 一种FPGA加速的天文数据无损压缩方案

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570562786

Yu Zheng, Yongxin Zhu, Yuefeng Song, Tianhao Nan, Wanyi Li

{"title":"A Lossless Astronomical Data Compression Scheme with FPGA Acceleration","authors":"Yu Zheng, Yongxin Zhu, Yuefeng Song, Tianhao Nan, Wanyi Li","doi":"10.1109/SOCC46988.2019.1570562786","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570562786","url":null,"abstract":"Bottlenecks are arising from the movement of the massive radio observation data of the Five Hundred Meter Aperture Spherical Radio Telescope (FAST), a path-finder project of the Square Kilometer Array radio telescope (SKA) which is the biggest radio telescope being constructed. There are a few lossy compression approaches proposed by astronomers to reduce the size of original observation data of FAST before the data are transferred from a telescope site to a remote data center. However, these lossy methods would lead to missing critical hidden scientific information. To solve the bottlenecks without losing critical hidden scientific information, we propose a lossless compression scheme in this paper to exploit the internal redundancy in astronomical data. In our scheme, an efficient compression algorithm is proposed to optimize the data preprocessing by improving the organization and structure of the astronomical dataset. As the first step towards system-on-chip (SOC) application specific chip design, we evaluate the feasibility of hardware acceleration of our scheme by implementing a prototype of the compression scheme on FPGA platform. The compression scheme has achieved superior performance in compression ratio and power consumption compared to other state-of-the-art researches in astronomy domain.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"52 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134554713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

SOCC 2019 Organizing Committee 2019年国际奥委会组委会

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088028

引用次数: 0

A Novel Test Vector Generation Method for Hardware Trojan Detection 一种新的硬件木马检测测试向量生成方法

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548271

Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, B. Sen

引用次数: 8