2019 32nd IEEE International System-on-Chip Conference (SOCC)最新文献_第9页

28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications 28nm 0.3V 1W2R亚阈值FIFO存储器，用于多传感器物联网应用

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555748

H. Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, W. Hwang, C. Chuang

{"title":"28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications","authors":"H. Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, W. Hwang, C. Chuang","doi":"10.1109/SOCC46988.2019.1570555748","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570555748","url":null,"abstract":"For energy-constrained multi-sensing IoT devices, ultra-low-power queueing is one of the critical event-driven design challenges to capture low-speed sensing data with various sampling frequencies. In this paper, 0.3V 1W2R sub-threshold FIFO memory is proposed for ultra-low-voltage operations using Schmitt-Trigger (ST) 12.5T SRAM bit-cell, ripple bitline structure and cross-point data-aware write wordline scheme. The ST 12.5T memory bit-cell not only increases hold static noise margin (HSNM) but also eliminates write half-select disturbance for robust sub-threshold operation. Secondly, an adaptive timing tracing circuitry and negative bit-line circuits are employed in the design for PVT variation-tolerant read operation and write ability enhancement. Thirdly, the proposed ripple bitline structure divides the bitline into several segments for ultra-low-voltage operations. Thus, the access time can be reduced apparently. Finally, a 4kb sub-threshold FIFO memory with the proposed multi-port ST 12.5T bit-cells is implemented by UMC 28nm HKMG technology. The proposed FIFO memory can execute one write and two read operations simultaneously for multi-sensor IoT applications. The average power and maximum write frequency are $4.01 mu mathrm{W}$ and 780kHz at 0.3V, respectively.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment 用于信号占空比调整的90 μW, 2.5 GHz高线性可编程延迟单元

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558550

Tobias Schirmer, M. Khafaji, Jan Plíva, F. Ellinger

{"title":"A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment","authors":"Tobias Schirmer, M. Khafaji, Jan Plíva, F. Ellinger","doi":"10.1109/SOCC46988.2019.1570558550","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558550","url":null,"abstract":"In this paper we introduce the design of a 2.5GHz low power CMOS inverter based 4-bit programmable delay cell with high linearity. The circuit is designed and optimized for the use in high-speed current-steering digital-to-analog converters. The basic architecture consists of a current-starved CMOS inverter delay element and a linear 4-bit digital-to-analog converter providing the reference current for the delay element. In addition, an analog low power pre-distortion circuit has been implemented which is modulating the output current of the DAC to compensate for the inherent nonlinearity of the delay element. Thus, the major drawback of state-of-the-art low power CMOS inverter based delay elements has been significantly mitigated whereas the power consumption is still 25 times less than for shunt-capacitor based architectures with comparable linearity. The delay cell including reference current generation and pre-distortion of the reference current only consumes 90 $mu W$ and is therefore well suited for low power applications. The proposed delay cell is implemented along with a CMOS pseudo-random bit sequence (PRBS) generator and a retiming flip-flop for providing a test data sequence at the input. Furthermore, a ${(50 Omega)}$ impedance matched buffer circuit has been implemented to measure the exact undistorted waveforms of the delay element at the output. The system is implemented and fabricated in a 22nm FD-SOI CMOS process.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114147655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reactive and Proactive Threat Detection and Prevention for the Internet of Things 物联网的被动和主动威胁检测和预防

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570574214

Matthew Hagan, S. Sezer, K. Mclaughlin

{"title":"Reactive and Proactive Threat Detection and Prevention for the Internet of Things","authors":"Matthew Hagan, S. Sezer, K. Mclaughlin","doi":"10.1109/SOCC46988.2019.1570574214","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570574214","url":null,"abstract":"The Internet of Things presents significant potential benefits to society. However, so too exists a multitude of threats, both those adapted from IT systems and newly created attacks that exploit devices, infrastructure, services and their users.This thesis contributes towards the security of the IoT from a device perspective. The first contribution is a new method for analysing network traffic behaviours. By enhancing profiling methods, a novel, real-time approach has been applied to detect complex network events, including threats that can evade detection by means such as regular expression. The second contribution explores a use case-based modelling that allows the specification of technical policies, from the security model, that enforce the intended functionality of the device. When implemented, such an approach can ensure that the system operates only as intended, regardless of security issues that may arise later. Finally, an enforcement mechanism is proposed at system bus level that can infer malicious activity and mitigate its effects. This approach has advantages over existing softwarebased solutions, in that it is implemented as a physically isolated hardware block. Each of the contributions is evaluated within a proposed connected car implementation, demonstrating the applicability of the research undertaken, within the IoT.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126222851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier 多通道跨阻放大器串扰噪声滤波器的设计

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570554632

Shinya Tanimura, A. Tsuchiya, R. Noguchi, Toshiyuki Inoue, K. Kishine

引用次数: 1

T2A: Low Power Design T2A:低功耗设计

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088093

引用次数: 0

T2B: System Level Design Optimization T2B:系统级设计优化

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/socc46988.2019.9088076

引用次数: 0

Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing 用于神经形态计算的具有自动时钟门控的功耗和面积高效路由器

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570548462

Junran Pu, V. P. Nambiar, Aarthy Mani, W. Goh, A. Do

{"title":"Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing","authors":"Junran Pu, V. P. Nambiar, Aarthy Mani, W. Goh, A. Do","doi":"10.1109/SOCC46988.2019.1570548462","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570548462","url":null,"abstract":"Network-on-Chip has been widely used as an interconnection fabric due to its high scalability. However, traditional router designs target multiprocessor systems-on-chips, and therefore needs to be improved according to the characteristics of neuromorphic computing. This paper proposes an ultra low power and low area router for neuromorphic computing. Clock gating technique is used to reduce router power consumption by reducing clock activities. The proposed router uses small FIFO based interface links to reduce router area. A modified round robin arbiter is proposed to reduce the router latency. The wormhole model is improved to make it better match neuromorphic computing applications. An ultra low power and small size ring oscillator was designed to provide a global clock to all design blocks. Experimental results show that the average power consumption of the proposed router is 0.26mW, and only 0.01mW when idle. It occupies a much smaller area (0.007 mm 2) compared to other router designs described in previous works. It can be seen from the experimental results that after the clock gating circuitry is added, the total power consumption of $a3 times3$ router array is significantly reduced, approximately $2.1 times$ lower when busy and $21 times$ lower when idle.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip Zynq-7000片上系统的多项式矩阵乘法加速

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570555424

Server Kasap, Soydan Redif, E. Wächter

引用次数: 0

An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform 动态利用CNN Winograd变换稀疏性的最小化FPGA加速设计

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570558495

Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao

{"title":"An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform","authors":"Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao","doi":"10.1109/SOCC46988.2019.1570558495","DOIUrl":"https://doi.org/10.1109/SOCC46988.2019.1570558495","url":null,"abstract":"To address the challenges of high computational complexity incurred in deep convolutional neural networks (CNNs), implementations by both the Fast Winograd Transform algorithm and the sparsity exploration method have been attempted in order to reduce the hardware operation overhead. Yet, the previous studies have been mainly concentrated on dealing with the fixed sparsity patterns of the weight filter. In this paper, we focus the effort specifically towards exploiting the characteristics of varying sparsity patterns existing in the input/output Activations of the Winograd-transformed network. To this end, a dynamically compressing approach for multiplication with the sparsity-changing matrix is proposed. Such a processing flow features in data indexing and restoring. Because they are dynamically generated during the inference process, the inputs/outputs are highly dependent on the actual data being processed. Unlike the static pattern of a weight matrix just requiring the offline compression, a real-time compression processor module is devised and employed to deal with the dynamic matrix pattern for updating online the inputs/outputs within FPGAs Block RAMs. In the next layer computation, only the valid data needs to be restored by following the necessary index information and broadcasting to those corresponding sparse weight matrices, which in turn generates the next batch inputs/outputs. The design has realized a typical CNN such as VGG on Xilinx Virtex 7 FPGA device for verification and achieves an overall performance of 629.4 GOPS. Meanwhile, the preliminary experimental results demonstrate 2.2 (up to 5.5) times improvement in terms of equivalent GOPS per DSP Block achieved with our adaptive sparsity exploitation approach, when compared to the other conventional counterparts.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Radar Transceivers for Inverse Synthetic Aperture Radar (ISAR) Imaging of Human Activity in 65nm CMOS 65nm CMOS反合成孔径雷达(ISAR)人体活动成像雷达收发器

2019 32nd IEEE International System-on-Chip Conference (SOCC) Pub Date : 2019-09-01 DOI: 10.1109/SOCC46988.2019.1570571692

Liheng Tang, Kai Tang, Zhongyuan Fang, Yisheng Wang, Bo Chen, Ting Guo, Chuanshi Yang, Yuanjin Zheng

引用次数: 0