多通道跨阻放大器串扰噪声滤波器的设计

Shinya Tanimura, A. Tsuchiya, R. Noguchi, Toshiyuki Inoue, K. Kishine
{"title":"多通道跨阻放大器串扰噪声滤波器的设计","authors":"Shinya Tanimura, A. Tsuchiya, R. Noguchi, Toshiyuki Inoue, K. Kishine","doi":"10.1109/SOCC46988.2019.1570554632","DOIUrl":null,"url":null,"abstract":"This paper discusses design of area effective crosstalk noise reduction for multi-channel transimpedance amplifiers. For parallel integration of optical receivers, noise via the power/ground lines is a serious issue. One of the noise reduction technique is an RC filter insertion, however systematic design is still unclear. We investigate how to determine the time constant of the RC filter. Since the time constant of RC filter affects the balance of the supply noise and the ground noise, the noise reduction becomes maximum at a certain time constant. We fabricated an 180-nm CMOS test chip of parallel TIAs with the RC filter. Measurement results confirm that an adequate time constant design maximize the noise reduction and the maximum reduction ratio is 38%.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier\",\"authors\":\"Shinya Tanimura, A. Tsuchiya, R. Noguchi, Toshiyuki Inoue, K. Kishine\",\"doi\":\"10.1109/SOCC46988.2019.1570554632\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses design of area effective crosstalk noise reduction for multi-channel transimpedance amplifiers. For parallel integration of optical receivers, noise via the power/ground lines is a serious issue. One of the noise reduction technique is an RC filter insertion, however systematic design is still unclear. We investigate how to determine the time constant of the RC filter. Since the time constant of RC filter affects the balance of the supply noise and the ground noise, the noise reduction becomes maximum at a certain time constant. We fabricated an 180-nm CMOS test chip of parallel TIAs with the RC filter. Measurement results confirm that an adequate time constant design maximize the noise reduction and the maximum reduction ratio is 38%.\",\"PeriodicalId\":253998,\"journal\":{\"name\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC46988.2019.1570554632\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC46988.2019.1570554632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

讨论了多通道跨阻放大器的区域有效串扰降噪设计。对于光接收器的并行集成,通过电源/地线的噪声是一个严重的问题。其中一种降噪技术是RC滤波器插入,但系统设计尚不清楚。我们研究了如何确定RC滤波器的时间常数。由于RC滤波器的时间常数影响电源噪声和地噪声的平衡,在某一时间常数时降噪最大。我们制作了一个带有RC滤波器的并行TIAs的180 nm CMOS测试芯片。测量结果表明,适当的时间常数设计可以最大限度地降低噪声,最大降噪率为38%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier
This paper discusses design of area effective crosstalk noise reduction for multi-channel transimpedance amplifiers. For parallel integration of optical receivers, noise via the power/ground lines is a serious issue. One of the noise reduction technique is an RC filter insertion, however systematic design is still unclear. We investigate how to determine the time constant of the RC filter. Since the time constant of RC filter affects the balance of the supply noise and the ground noise, the noise reduction becomes maximum at a certain time constant. We fabricated an 180-nm CMOS test chip of parallel TIAs with the RC filter. Measurement results confirm that an adequate time constant design maximize the noise reduction and the maximum reduction ratio is 38%.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信