Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications

Abstract

We propose a multicore power balancing technique by configuring data routing paths in the 9-core Network-on-Chip (NoC) based platform for hardware security applications, particularly for differential power analysis (DPA) countermeasures. There are three degrees of configurability to hide the leaked data. First, the cores are flexibly-programmable to perform AES operation and dummy operations to moderate the power dissipation. Second, the NoC routers are also flexibly-programmable, further enhancing the power moderation. Third, the cores and their associated routers feature individual controllable clock frequencies to moderate the time that leaks data. These three configurable features collectively balance the power dissipation and enable the time moderation to resist DPA. The 9-core platform IC occupies $\sim$1.9 mm2, operates up to 100MHz @1.2V and dissipates 2.46mW @100MHz power. When running Advanced Encryption Standard (AES) operation, the normalized energy deviation (NED) is undesirable high at 0.21 for power-on (1 core + 1 router). By applying the multicore power balancing technique, the NED reduces by $\sim$52% when increasing the number of operating routers from 1 to 5, i.e. (1 core + 5 routers), and reduces by $\sim$73% when increasing the number of operating cores from 1 to 4, i.e. (4 cores + 4 routers).