A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL

Abstract

In the paper, a 3Gb/s clock and data recovery (CDR) is presented for high-speed embedded-clock interconnects in LCD drivers. The CDR consists of a decision circuit for realizing regeneration, and a clock recovery circuit for realizing retiming. The proposed CDR combines the delay-locked and phase-locked loops to improve the jitter peaking. Implemented in 0.18-$\mu$m CMOS technology, the recovered clocks have 5.27ps peak-to-peak jitter at 100MHz clock frequency, and the recovered data have 5.34ps peak-to-peak jitter at 2.7-Gb/s data rate. This work consumes 72.52mW with 1.8V power supply.