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引用次数: 1
摘要
介绍了一种采用快速锁相技术的10ghz全数字锁相环频率合成器。提出的快速锁定技术使用两种相互优化的机制。一种是提高频率跟踪能力，另一种是采用频率误差检测方法提高频率跟踪效率。该ADPLL合成器采用0.18 um CMOS工艺制作，工作频率为9.4 ~ 10.4 GHz。总功耗为30.6mW，供电电压为1.8V。当跳频距离为400 MHz时，加快锁和不加快锁的锁定时间分别为0.88 us和190 us。
A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection
This paper presents a 10-GHz all-digital phaselocked loop (ADPLL) frequency synthesizer with a fast-locked technique. The proposed fast-locked technique uses two mechanisms that optimize each other. One enhances the capability of frequency-tracking, the other uses a method for detecting frequency-error to improve the efficiency of frequencytracking. The ADPLL synthesizer is fabricated in a 0.18 um CMOS process, and its operating frequency is from 9.4 GHz to 10.4 GHz. The total power consumption is 30.6mW with 1.8V supply voltage. The locked time is 0.88 us and 190 us with and without the fast-locked technique when the frequency hopping distance is 400 MHz, respectively.
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