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2015 International 3D Systems Integration Conference (3DIC)最新文献

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Cost modeling and analysis for the design, manufacturing and test of 3D-ICs 3d集成电路设计、制造和测试的成本建模和分析
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334603
A. Grünewald, M. Wahl, R. Brück
{"title":"Cost modeling and analysis for the design, manufacturing and test of 3D-ICs","authors":"A. Grünewald, M. Wahl, R. Brück","doi":"10.1109/3DIC.2015.7334603","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334603","url":null,"abstract":"In the last years 3D-Integration has emerged as one possible solution to develop heterogeneous systems with a preferably low feature-size. Along with the variety of possibilities on how to vertically integrate two or more dies, many aspects including design, choice of technology and cost have to be considered. The increase of complexity emphasizes the need to consider technology and test issues already at the design stage. Going along with this, economical aspects have to be regarded as well to be able to decide the feasibility of the system at the beginning of the development process. Therefore, first domains that generate cost are named and analyzed. After that, this paper proposes comprehensive cost modeling for 3D-ICs, which covers the whole production chain from the design stage to final test. The cost model has been implemented in the tool COMOA-3D which is able to analyze the costs of the different parts and to compare different process and test flows, which can be imported into the tool.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122800048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thermal stability of electroplated copper thin-film interconnections 电镀铜薄膜互连的热稳定性
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334560
Pornvitoo Rittinon, Ken Suzuki, H. Miura
{"title":"Thermal stability of electroplated copper thin-film interconnections","authors":"Pornvitoo Rittinon, Ken Suzuki, H. Miura","doi":"10.1109/3DIC.2015.7334560","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334560","url":null,"abstract":"There were local distributions of the crystallinity and resistance in a test interconnection. The local resistance of the interconnection varied with the local crystallinity. The maximum temperature appeared in the local area with the minimum crystallinity, in other words, the area with the highest resistance under the application of high current density of 10 MA/cm2. Thus, local high Joule heating occurred in the test interconnection due to the local variation of the crystallinity of the interconnection. The maximum temperature decreased from about 170°C to 140°C when the average crystallinity (IQ value which was obtained from EBSD analysis) increased from 3000 to 4100. This decrease of the maximum temperature can be explained by the decrease of Joule heating under the application of a fixed current density. This decrease of the maximum temperature increased the long-term reliability of the interconnections drastically.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121203663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilane 高品质低温(≤120°C)有机硅烷制备的PECVD-SiN薄膜
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334600
Hiroshi Taka, Katsumasa Suzuki, N. Tsujioka, S. Murakami
{"title":"Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilane","authors":"Hiroshi Taka, Katsumasa Suzuki, N. Tsujioka, S. Murakami","doi":"10.1109/3DIC.2015.7334600","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334600","url":null,"abstract":"We obtained high-quality PECVD-SiN films deposited under 120°C using organosilane precursor. The SiN film has low hydrogen content and low BHF etching rate. In addition, SiN film properties did not change after pressure cooker test (PCT: 120°C, 0.2 MPa, 6 hours). The low-temperature deposition process for SiN films hold promise for improving 3DIC manufacturing process.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123435750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner 二次蚀刻硅方法的通孔-最后通过硅通孔与聚苯乙烯- ht衬垫
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334611
B. T. Tung, N. Watanabe, M. Aoyagi, K. Kikuchi
{"title":"Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner","authors":"B. T. Tung, N. Watanabe, M. Aoyagi, K. Kikuchi","doi":"10.1109/3DIC.2015.7334611","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334611","url":null,"abstract":"In this paper, an alternative fabrication approach to realize a via-last through-Si-via (TSV) for 3D chip stacking is proposed. Two deep silicon etching process (BOSCH) are implemented respectively for TSV's liner and metal layers in order to avoid the critical process to open the contact at the bottom of Si via. Moreover, Parylene-HT is utilized for achieving highly uniformity, high-step-coverage liner. Vias was filled with a solder by a vacuum-assisted filling system. TSVs with dimensions of 6 μm × 22 μm (diameter×height) with 1.5-μm-thick Parylene-HT insulation layer were demonstrated using the proposed approach. Inspection of the fabricated TSV structure is conducted and results are reported.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133672437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
3D integration: Applications and market trends 3D集成:应用和市场趋势
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334567
R. Beica
{"title":"3D integration: Applications and market trends","authors":"R. Beica","doi":"10.1109/3DIC.2015.7334567","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334567","url":null,"abstract":"3D integration using through-silicon-via (TSV) technology can bring several advantages over traditional integration techniques, such as System-on-Chip (SOC): shorter connections, increased interconnect density and bandwidth, lower power consumption and enhanced integration flexibility. Such advantages have already been shown for various products, from CMOS Image Sensors and MEMS devices in the consumer market, to FPGAs and more recently, memories for high-end applications. This paper will provide an overview of the different applications of 3D integration using TSV technology, including product announcements, reverse engineering and worldwide patent activities, highlighting the most active players and their activities.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"13 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127425448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Path to 3D heterogeneous integration 3D异构集成路径
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334469
D. Green, C. L. Dohrman, J. Demmin, Tsu-Hsi Chang
{"title":"Path to 3D heterogeneous integration","authors":"D. Green, C. L. Dohrman, J. Demmin, Tsu-Hsi Chang","doi":"10.1109/3DIC.2015.7334469","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334469","url":null,"abstract":"The DARPA Microsystems Technology Office is developing revolutionary materials, devices, and integration techniques for meeting the performance requirements for advanced microwave and RF systems. The DARPA Compound Semiconductor Materials on Silicon (COSMOS) program focused on the development of new methods to tightly integrate compound semiconductor (CS) technologies within state-of-the-art silicon CMOS circuits in order to achieve unprecedented circuit performance levels. The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program is continuing that work by developing heterogeneous integration processes to intimately combine advanced CS devices, as well as other emerging materials and devices, with high-density silicon CMOS technology. Taken together, these programs are addressing many of the critical challenges for next-generation RF modules and seek to revolutionize DoD capabilities in this area.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116348288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Active Si interposer for 3D IC integrations 用于3D集成电路的有源硅中间体
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334619
Joungho Kim
{"title":"Active Si interposer for 3D IC integrations","authors":"Joungho Kim","doi":"10.1109/3DIC.2015.7334619","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334619","url":null,"abstract":"3D IC is becoming the most promising solution for the future low power, high bandwidth, and small size semiconductor systems including computer, mobile, and network systems. In the 3D IC, Si interposer can effectively serve as the high density and high bandwidth interconnections between the chips on the interposers. Si interposer for HBM (High-bandwidth Memory Module) is an example. In this paper, we propose a new novel interposer structure which is called as “Active interposer.” In the proposed active interposer scheme, passive devices and active circuits are integrated together to enhance the signal integrity, and power integrity, and to lower power consumptions. The actives circuits in the Si interposer include equalizer, clock distribution network as well as DC-DC converter circuit. Also, wireless power delivery network can be added to reduce the number and space of P/G balls and vias.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128270886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Warpage analysis of organic substrates for 2.1D packaging 2.1D封装用有机衬底翘曲分析
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334586
S. Kohara, K. Okamoto, H. Noma, K. Toriyama, H. Mori
{"title":"Warpage analysis of organic substrates for 2.1D packaging","authors":"S. Kohara, K. Okamoto, H. Noma, K. Toriyama, H. Mori","doi":"10.1109/3DIC.2015.7334586","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334586","url":null,"abstract":"2.1D packaging is a potential low cost alternative to 2.5D packaging. Instead of using silicon/glass interposers, in 2.1D package, a high-density wiring layer is on the chip side of the substrate acting as an interposer. One of the challenges for 2.1D packaging is the thermal deformation of organic substrates due to their highly asymmetric structure. In this report, we analyzed the thermal warpage of 2.1D substrates by finite element method. The analyses are done on a 3-2-3 build-up layer structure with high-density wiring layers on the chip mounting side, since it has potential applications as multi-chip package products. The analysis showed that the warpage of the test substrate is 250μm for the substrate of 47.5mm×47.5mm in size. The adjustment of the Cu loading ratio of the back build-up layers only reduces the warpage by 17%. We propose a structure in which a circuitry layer and an insulating via layer are added to the back side of the substrate for the warpage reduction. The thickness of the circuitry layer is set equal to the total thickness of the high density circuitry layers. The thickness of via layer is also set equal to the total thickness of the insulating layers between the high-density wiring layers. However we found that the optimum Cu loading ratio for the adjustment circuitry layer is lower than the average Cu loading ratio for the high-density wiring layers by 20 to 40 %. The analysis showed that the proposed substrate structure reduces the warpage significantly.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131802665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration 三维集成中硅通孔铜泵送对BEOL可靠性的电气研究
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334581
Chuan-An Cheng, R. Sugie, T. Uchida, Kou-Hua Chen, C. Chiu, Kuan-Neng Chen
{"title":"Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration","authors":"Chuan-An Cheng, R. Sugie, T. Uchida, Kou-Hua Chen, C. Chiu, Kuan-Neng Chen","doi":"10.1109/3DIC.2015.7334581","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334581","url":null,"abstract":"It is crucial for Cu TSV to be reliable at the back-end-of-line (BEOL) procedure particularly at high temperature process step. Any unreliable Cu TSV may cause residual from thermal stress due to the mismatch of the coefficient of thermal expansion. Therefore, it is important to investigate on the behavior of Cu pumping whether it will affect the electrical performance in BEOL integration. Two sets of Cu pumping with pitch 30 μm and 40 μm were annealed to measure their resistance at the temperature lower than 250°C. Based on the results, the narrow pitch of 30μm can be applied in post via last process below 250°C for BEOL procedure in 3D integration.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon interposer platform with low-loss through-silicon vias using air 使用空气的低损耗硅通孔硅中间平台
2015 International 3D Systems Integration Conference (3DIC) Pub Date : 2015-08-01 DOI: 10.1109/3DIC.2015.7334621
Hanju Oh, G. May, M. Bakir
{"title":"Silicon interposer platform with low-loss through-silicon vias using air","authors":"Hanju Oh, G. May, M. Bakir","doi":"10.1109/3DIC.2015.7334621","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334621","url":null,"abstract":"A silicon interposer platform featuring low-loss through-silicon vias (TSVs) using air is proposed and demonstrated. The proposed low-loss TSVs are fabricated by partially etching silicon between the signal and ground TSVs. High-frequency characterization in the 10 MHz-to-20 GHz frequency range demonstrates that the proposed TSVs reduce capacitance by 63.2% at 20 GHz compared to conventional TSVs.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129180081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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