2005 13th International Conference on Advanced Thermal Processing of Semiconductors最新文献

Ultra shallow junctions formed by sub-melt laser annealing 亚熔体激光退火形成的超浅结

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-12-01 DOI: 10.1063/1.2401478

A. Falepin, T. Janssens, S. Severi, W. Vandervorst, S. Felch, V. Parihar, A. Mayur

引用次数: 4

Infrared emittance measurements at NIST NIST的红外发射度测量

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-05 DOI: 10.1109/RTP.2005.1613711

L. Hanssen, B. Tsai, S. Mekhontsev

{"title":"Infrared emittance measurements at NIST","authors":"L. Hanssen, B. Tsai, S. Mekhontsev","doi":"10.1109/RTP.2005.1613711","DOIUrl":"https://doi.org/10.1109/RTP.2005.1613711","url":null,"abstract":"A new capability for the measurement of the temperature-dependent emittance of specular samples in the near infrared spectral region has been developed in NIST's infrared spectrophotometry laboratory to provide emittance measurements and standards for a broad range of applications including rapid thermal processing (RTP). Our approach employs the indirect measurement of reflectance and transmittance measurements to obtain emittance. A vacuum goniometer system controls the sample environment and measurement geometry. The main system, including the sample, is contained in a vacuum chamber that enables characterization of materials otherwise susceptible to oxidation. Details of the lasers, sources, detectors, and other optics in the system are given. The system has initially been used to characterize the spectral emittance (by reflectance) of a variety of semiconductor wafer samples including bare silicon and silicon substrates coated with SiO 2, Si3N4, and polysilicon films. The spectral range for these measurements is from 600 nm to 1100 nm, where Si is opaque; the temperature range is ambient to 800degC. The results are analyzed and compared with those predicted by several models from the literature","PeriodicalId":253409,"journal":{"name":"2005 13th International Conference on Advanced Thermal Processing of Semiconductors","volume":"16 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120852000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Near-ideal implanted shallow-junction diode formation by excimer laser annealing 准分子激光退火制备近理想植入浅结二极管

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613688

V. Gonda, A. Burtsev, T. Scholtes, L. Nanver

引用次数: 11

Multi-scale simulation of ultra-fast radiation anneal processes for robust process implementation 超快辐射退火过程的多尺度模拟及其鲁棒性实现

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613698

K. L. Knutson, Jack Hwang, R. James, P. Keys, S. Talukdar, S. Cea

引用次数: 0

CMOS challenges of keeping up with Moore's Law CMOS跟上摩尔定律的挑战

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613679

M. Orlowski

{"title":"CMOS challenges of keeping up with Moore's Law","authors":"M. Orlowski","doi":"10.1109/RTP.2005.1613679","DOIUrl":"https://doi.org/10.1109/RTP.2005.1613679","url":null,"abstract":"As the conventional scaling of CMOS technology is reaching its physical limitations, new materials and processes hold promise of giving CMOS a new lease on life. In order to turn an opportunity into a reality, the semiconductor industry is confronted with a daunting task of managing and co-integrating an unprecedented confluence of innovative approaches: high-k dielectric materials (HfO2, HfSiON) possibly to be formed by atomic layer deposition (ALD) are needed to curb gate leakage current and thus power consumption; metal gates (TiN, TaC, MoN) are requisite for optimization of threshold voltages for MOSFETs allowing low voltage operation; engineered substrates (sSOI, SiGeOI, GOI, dual substrate orientation) along with uni-axial and biaxial stressor techniques are required to keep the channel carrier mobility high to effect further performance gains; higher-mass dopant species (B10H14) are being synthesized to enable ultra-shallow junction; new dopant activation techniques (spike, pulsed laser anneals) and new contact metallization (NiSi) are pursued to induce high dopant activation and low contact resistance, respectively. The introduction of these innovative approaches is coming at a high price, though: the new materials pose new set of concurrent, multifarious challenges both for unit process development and for process integration. This paper reviews the technology opportunities and focuses on the trade-offs between performance benefits, scalability, complexity, co-integrability (including prominently spatial and temporal constraints on thermal processing), and impact on metrology, yield, and reliability","PeriodicalId":253409,"journal":{"name":"2005 13th International Conference on Advanced Thermal Processing of Semiconductors","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114866168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Calibration of a low-temperature cable-less lightpipe pyrometer on the NIST post-exposure bake test bed 在NIST曝光后烘烤试验台上校准低温无电缆光管高温计

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613709

B. Tsai, K. Kreider, W. Kimes

引用次数: 0

High Productivity Single Wafer Radical Oxidation System 高生产率单晶片自由基氧化系统

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1614330

Y. Yokota, A. Tjandra, Kai Ma, M. Sanaka, K. Moritz, R. S. Sharma, H. Forstner

{"title":"High Productivity Single Wafer Radical Oxidation System","authors":"Y. Yokota, A. Tjandra, Kai Ma, M. Sanaka, K. Moritz, R. S. Sharma, H. Forstner","doi":"10.1109/RTP.2005.1614330","DOIUrl":"https://doi.org/10.1109/RTP.2005.1614330","url":null,"abstract":"This paper introduces a high productivity single wafer radical oxidation system developed for ≤90nm device node. Today's semiconductor device manufacturers face dual challenges of increased technical complexity at virtually every process step, and fast introduction of new products with minimal cost. Up until now, furnaces have satisfied the thermal oxidation requirements in most fabs. The scaling of advanced devices requires higher quality oxides, tighter process control, and smaller thermal budgets at significantly reduced overall processing cost. RadOx™processes have already demonstrated advantages in a variety of applications for current devices, and have been well accepted by many device manufacturers. The availability of RadOx™processes on a reliable, small-footprint platform with reduced pressure capability will enable the technical advantages of single-wafer radical oxidation and the manufacturing requirements for today's economic environment. The Applied Vantage®platform has already gained wide acceptance for implant and silicide anneals, and with the introduction of Applied Vantage®RadOx™, the suite of applications is extended to include reduced pressure processes such as RadOx™. Process and system performance will be presented in this paper with emphasis on the chamber & platform technology elements that enable single-wafer radical oxidation on an industry-proven, cost-effective platform.","PeriodicalId":253409,"journal":{"name":"2005 13th International Conference on Advanced Thermal Processing of Semiconductors","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126507623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The FDTD computation of electromagnetic wave scattering from surfaces 电磁波表面散射的FDTD计算

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613718

K. Fu, P. Hsu

{"title":"The FDTD computation of electromagnetic wave scattering from surfaces","authors":"K. Fu, P. Hsu","doi":"10.1109/RTP.2005.1613718","DOIUrl":"https://doi.org/10.1109/RTP.2005.1613718","url":null,"abstract":"The radiative properties of engineering surfaces with microscale surface textures (patterned or random roughness and coating) are of fundamental and practical importance. In the rapid thermal processing or arc/flash-assisted heating of silicon wafers, the control of energy deposition through radiation and the surface temperature measurement using optical pyrometry require in-depth knowledge of the surface radiative properties. These properties are temperature, wavelength, and surface texture dependent. It is important that these properties can be modeled and predicted with reasonable accuracy. This study builds the foundation by solving the Maxwell equations that describe the electromagnetic wave reflection from the one-dimensional random roughness surfaces. The surface height conforms to the normal distribution, i.e., a Gaussian probability density function distribution. The models produce very accurate bi-directional reflectivity with its accuracy limited by the numerical scheme. The numerical algorithm of Maxwell equations' solution is based on the well-developed finite difference time domain (FDTD) scheme and near-to-far-field transformation. Various computational modeling issues that affect the accuracy of the predicted properties are quantified and discussed. The predicted properties were compared and found in good agreement with the published work","PeriodicalId":253409,"journal":{"name":"2005 13th International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128887722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ni/sub 2/Si and NiSi formation by low temperature soak and spike RTPs 低温浸泡和脉冲rtp形成Ni/sub 2/Si和NiSi

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613706

Eun-Ha Kim, H. HaIi Forstner, M. Foad, N. Tam, S. Ramamurthy, P. Griffin, J. Plummer

{"title":"Ni/sub 2/Si and NiSi formation by low temperature soak and spike RTPs","authors":"Eun-Ha Kim, H. HaIi Forstner, M. Foad, N. Tam, S. Ramamurthy, P. Griffin, J. Plummer","doi":"10.1109/RTP.2005.1613706","DOIUrl":"https://doi.org/10.1109/RTP.2005.1613706","url":null,"abstract":"As the size of metal oxide semiconductor devices continues to be scaled down to sub-90 nm, novel materials must be integrated successfully in order to meet the technical demands. Nickel silicide (NiSi) is being considered as an alternative material to cobalt silicide (CoSi2) for the self-aligned silicide process, because it forms at lower temperatures with less silicon consumption and is compatible with SiGe. In order to prevent excessive silicidation in narrow gate lines and at the edges of source/drain regions, NiSi integration requires limiting silicidation kinetics via reduced thermal budgets followed by forming the low resistance phase. This paper focuses on the low temperature regime of the Ni-Si reaction through the use of soak RTP at 300degC and spike RTP at 300 ~ 400degC. In order to study the formation of Ni2Si and NiSi and the transformation from Ni2Si to NiSi, the silicide films are characterized by Rs sheet resistance measurements, XRD for phase identification, and TEM for microstructure. The intermediate phase of Ni2Si is formed at 270degC and its growth is observed with increasing anneal time. At temperatures above 300degC, the NiSi phase is found in addition to the Ni2Si phase, and the transformation from Ni2Si to NiSi is observed. The sequence of the Ni2Si-NiSi transformation involves the initial formation of NiSi and the change in the alignment of the crystal planes as the low resistance phase of NiSi forms. Two RTP schemes, soak RTP and spike RTP, follow parallel trends in the sequence of the Ni2Si-NiSi transformation with marked differences in the reaction kinetics","PeriodicalId":253409,"journal":{"name":"2005 13th International Conference on Advanced Thermal Processing of Semiconductors","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131864304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Process influences on the microstructural and electrical properties of rapid thermal chemical vapor deposited polysilicon 工艺对快速热化学气相沉积多晶硅显微结构和电性能的影响

2005 13th International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2005-10-04 DOI: 10.1109/RTP.2005.1613715

J. Nakos

引用次数: 1